Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-08-23
2002-12-03
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C156S345420, C216S037000, C216S067000, C216S079000, C438S719000, C438S734000, C438S735000
Reexamination Certificate
active
06489248
ABSTRACT:
BACKGROUND
The present invention relates to etching of a substrate in a plasma of process gas.
Electronic devices, such as integrated circuits, are formed by deposition, growth (such as by oxidation, nitridation, etc.) and etching of material on a substrate. In a typical etching process, a patterned etch-resistant mask is formed on the substrate by a conventional photolithographic process, and thereafter, exposed portions of the substrate are etched away with energized gases. In the etching process, a reactive gas is introduced into a chamber and is supplied with electromagnetic energy, such as microwave or radio frequency energy, to form an energized gas, such as a plasma, to etch the substrate. In addition, a biasing voltage may be applied to the plasma to energize charged plasma species to provide more anisotropic etching.
In the etching process, it is desirable to control the dimensions of the features being etched, and it also desirable to etch features, such as openings or trenches, with smooth vertical sidewalls. However, conventional etching processes often result in non-uniform etching rates and microloading effects across the substrate. Microloading is a general term used to describe undesirable variations in etch rates, feature shapes, or other etching attributes, from one etched feature to another and across the substrate. For example, the etching rates of the etched holes may vary between small diameter holes which have a high aspect ratio and large diameter holes or open spaces. As another example, the shape or etching rates of the etched features may vary from regions of the substrate having a high density of features (dense feature regions) to regions having relatively few and isolated features (isolated feature regions). Critical dimension microloading may also arise from the variations in critical dimensions of the etched features, the critical dimensions (CD) being those dimensions that are used to calculate the electrical properties of the etched features in the design of integrated circuits. For example, the cross-sectional area of an interconnect line or contact is a critical dimension that should be close to predetermined dimensions to provide the desired electrical resistance.
Accordingly, it is desirable to etch features, such as holes and interconnect lines, across the substrate at uniform and reproducible etch rates. It is further desirable to reduce variations in the etching rate of the high aspect ratio holes relative to open spaces on the substrate. It is also desirable to obtain etched features having uniform and predictable shapes.
SUMMARY
A method of processing a substrate in a process chamber having process electrodes comprises providing a substrate in the process chamber, the substrate comprising a patterned mask and exposed openings, in a plasma ignition stage, providing a process gas in the process chamber and energizing the process gas by maintaining the process electrodes at a plasma ignition bias power level, in an etch-passivating stage, forming an etch-passivating material on at least portions of the substrate by maintaining the process electrodes at an etch-passivating bias power level, and in an etching stage, etching the exposed openings on the substrate by maintaining the process electrodes at an etching bias power level.
A substrate processing apparatus comprises a process chamber having a support capable of receiving a substrate, wherein the substrate comprises a patterned mask and exposed openings, a gas supply capable of introducing a process gas into the process chamber, a gas energizer to energize the process gas, the gas energizer comprising process electrodes, and a controller adapted to (i) in a plasma ignition stage, maintain the process electrodes at a plasma ignition bias power level to ignite a plasma, (ii) in an etch-passivating stage, maintain the process electrodes at an etch-passivating bias power level to form an etch-passivating material on at least portions of the substrate, and (iii) in an etching stage, maintain the process electrodes at an etching bias power level to etch the exposed openings on the substrate.
REFERENCES:
patent: 4392932 (1983-07-01), Harra
patent: 4521275 (1985-06-01), Purdes
patent: 4579623 (1986-04-01), Suzuki et al.
patent: 4613400 (1986-09-01), Tam et al.
patent: 4678540 (1987-07-01), Uchimura
patent: 4698128 (1987-10-01), Berglund et al.
patent: 4702795 (1987-10-01), Douglas
patent: 4717448 (1988-01-01), Cox et al.
patent: 4741799 (1988-05-01), Chen et al.
patent: 4784720 (1988-11-01), Douglas
patent: 4790903 (1988-12-01), Sugano et al.
patent: 4795529 (1989-01-01), Kawasaki et al.
patent: 4844767 (1989-07-01), Okudaira et al.
patent: 4855017 (1989-08-01), Douglas
patent: 4902377 (1990-02-01), Berglund et al.
patent: 5047115 (1991-09-01), Charlet et al.
patent: 5242536 (1993-09-01), Schoenborn
patent: 5256245 (1993-10-01), Keller et al.
patent: 5271799 (1993-12-01), Langley
patent: 5302241 (1994-04-01), Cathey, Jr.
patent: 5332653 (1994-07-01), Cullen et al.
patent: 5362526 (1994-11-01), Wang et al.
patent: 5498312 (1996-03-01), Laermer et al.
patent: 5501893 (1996-03-01), Laermer et al.
patent: 5545290 (1996-08-01), Douglas et al.
patent: 5591664 (1997-01-01), Wang et al.
patent: 5719089 (1998-02-01), Cherng et al.
patent: 5726102 (1998-03-01), Lo
patent: 5895273 (1999-04-01), Burns et al.
patent: 5942446 (1999-08-01), Chen et al.
patent: 6025268 (2000-02-01), Shen
patent: 6090717 (2000-07-01), Powell et al.
patent: 6121154 (2000-09-01), Haselden et al.
patent: 6127273 (2000-10-01), Laermer et al.
patent: 6291357 (2001-09-01), Zhang et al.
patent: 3613181 (1987-10-01), None
patent: 3940083 (1991-06-01), None
patent: 4202447 (1992-07-01), None
patent: 4204848 (1992-08-01), None
patent: 9910922 (1999-03-01), None
patent: 200951 (1986-04-01), None
patent: 298204 (1988-04-01), None
patent: 363982 (1989-10-01), None
patent: 383570 (1990-02-01), None
patent: 497023 (1991-01-01), None
patent: 822582 (1997-07-01), None
patent: 2290413 (1995-06-01), None
patent: 61156100 (1986-07-01), None
patent: 61260738 (1986-11-01), None
patent: 3129820 (1991-06-01), None
Mahi Y. Arnal and C. Pomot, The etching of silicon in diluted SF 6 plasmas: Correlation between the flux of the incident species and the etching kinetics, 8257B Journal of Vacuum Science & Technology/Part B, May/Jun. (1987) pp. 657-666,.
C.C. Tin, T.H. Lin and Y. Tzeng, Effects of RF Bias on Remote Microwave Plasma Assisted Etching Of Silicon in SF 6, 1046 Journal of the Electrochemical Society 138, Oct. (1991), No. 10, pp. 3094-3100.
K. Tsujimoto, S. Tachi, K. Ninomiya, K. Suzuki, S. Okudaira and S. Nishimatsu, A New Side Wall Protection Technique in Microwave Plasma Etching Using a Chopping Method, Central Research Laboratory, Hiachi Ltd.
I.W. Rangelow, High-resolution tri-level process by downstream-microwave RF-biased etching, 180/SPIE vol. 1392 Advanced Techniques for Integrated Circuit Processing (1990), University of Kassel, Heinrich Plett-StraBe 40, D-3500-Kassel, W. Germany.
35thApplied physics-related joint lecture, p. 28, g-5, Mar. 28, 1998.
S. Okudaira, et al., Plasma Research Group, Kenki Gakkai, (Electrical Engineering Society), EP-89, 1989.
Adisaputro Ida Ariani
Kim Kwang-Soo
Wang Ruiping
Zhang Luke
Bach Joseph
Janah Ashok
Powell William A.
LandOfFree
Method and apparatus for etch passivating and etching a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for etch passivating and etching a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for etch passivating and etching a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2933343