Method and apparatus for estimating parasitic capacitance

Details Method and apparatus for estimating parasitic capacitance Method and apparatus for estimating parasitic capacitance

2007-08-21

2007-08-21

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C703S002000, C703S005000, C703S014000

Reexamination Certificate

active

10935765

ABSTRACT:
One embodiment of the present invention provides a system for estimating parasitic capacitance for an integrated circuit. During operation, the system reads a technology file, which describes the composition of a vertical cross-section of the integrated circuit. Next, the system reads a design file, which specifies the layout of the integrated circuit. The system then identifies a set of dielectric configurations based on information contained in the technology file. It then computes Green's function for each of these configurations. Next, the system estimates a parasitic capacitance using information contained in the design file and using the set of Green's functions.

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