Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-08-05
2002-02-05
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06345379
ABSTRACT:
FIELD OF INVENTION
This invention is related to the field of designing digital circuits. In particular, this invention is related to estimating the power that would be dissipated by a digital circuit.
DESCRIPTION OF THE RELATED ART
Power as a Factor in Digital Design
With the advent of portable applications such as notebook computers, cellular phones, palm-top computers etc., there is a growing emphasis in the hardware design community for Computer Aided Design (CAD) tools for low power IC design. Today, the predominant differentiator of portable applications in the marketplace is their “battery life” not their performance. Even designers of high performance ICs are expressing a need for such tools because clocks are running faster, chips are getting denser and packaging and thermal control are playing a dominant role in determining the cost of such ICs. The cost of upgrading from a plastic packaging, which typically can handle peak power dissipation of approximately 1 Watt, to a ceramic packaging, which has lower thermal resistivity, can be roughly a tenfold increase in cost.
Managing Power in a Typical Digital Design Flow
An important part of minimizing power dissipated by a system is reducing the power dissipated by the chips in the system. Because fabricating chips is expensive and time consuming, a chip designer often uses CAD tools to estimate the power dissipation of a particular design before actually fabricating the chip in silicon. From this power estimate the designer can modify the design before fabrication to reduce the power dissipation. However, the conventional method of estimating power at the design phase has its own problems.
FIG. 1
is a flow diagram illustrating a conventional design used by a designer to reduce the power dissipated on a chip.
A general description of the process and techniques used to design and analyze digital designs can be found in the
Principles of CMOS VLSI Design
by Neil H. E. Weste and Kamran Eshraghian, published in 1992 by Addison-Wesley Publishing Company, ISBN 0-201-53376-6, which is hereby incorporated by reference. Another overview of the design process can be found in U.S. patent application Ser. No. 08/226,147 entitled “Hardware Description Language Source Debugger” by Gregory, et al, filed on Apr. 12, 1994, which is hereby incorporated by reference. Another overview of the design process can be found in co-pending U.S. application Ser. No. 08/253,470 entitled “Architecture and Methods for A Hardware Description Language Source Level Debugging System”, filed on Jun. 3, 1994, which is hereby incorporated by reference. In
FIG. 1
, the general design flow begins with a semiconductor vendor constructing a library of cells, as shown in step
1000
. These cells perform various combinational and sequential functions. The semiconductor vendor, with the help of CAD tools, characterizes the electrical behavior of those cells. For example, the vendor provides estimates of the delay through each cell and how much substrate area the cells will occupy. This establishes a library of components that a designer can use to build a complex chip.
Recently, semiconductor vendors have also started characterizing the power dissipation of the library cells as a single static value. However, the power dissipation of a cell is a complex function of the loading on the cell's output(s), toggle rates of the cell's inputs and outputs, and transition times of the cell's inputs. Without a model that allows them to capture the dependence of the cell's power on those three principal factors, semiconductor vendors have instead resorted to characterizing a single static value normally in units of Joules per KHz). Because this model ignores all of the key factors that influence power dissipation, its results are only utilized as very rough estimates. In step
1010
, the designer specifies the functional details of the design. One method that the designer can use to describe the design is to write a synthesis source description in a Hardware Description language (HDL). The designer could also describe the design with a schematic capture tool bypassing steps
1010
and
1020
.
In step
1020
, the CAD system creates a network of gates that implements the function specified by the designer in step
1010
. This is commonly referred to as the synthesis step. Importantly, at this step, the CAD system has information about which cells are going to be used and how the cells will be connected to each other.
In step
1030
, the CAD system determines where the cells identified in step
1020
will be placed on the chip substrate, and how the connections between the cells will be routed on the substrate. This is commonly referred to as the layout or “Place & Route” step. This step establishes the physical layout of the chip. Ordinarily, it requires a significant amount of computation time.
In step
1035
, tie CAD system extracts a transistor level netlist for the design from the layout.
In step
1040
, the CAD system estimates the power used by the chip from the netlist extracted in step
1035
. This is done by applying a representative set of input stimuli to a simulation model derived from the netlist. Constructing the input stimuli and simulating the stimuli requires a significant amount of computation time. This detailed simulation, however, can produce an accurate estimate of the power that the final chip will dissipate. The accuracy of the estimates depends on how representative the input stimuli set is compared to the actual operation of the design. Sometimes, the stimuli set is selected for purposes of functional testing of the design in which case the stimuli set will not be representative of the normal operation of the design.
In step
1050
, the designer determines whether the power dissipated by the chip is sufficiently low to meet the designer's needs with respect to battery life and the package used. If not, the designer modifies the degign in step
1060
, and repeats steps
1020
,
1030
, and
1040
. If the power dissipation is within bounds, and the design meets all other requirements, the chip is fabricated in step
1070
.
Limitations of Existing Power Estimation Methods
The general design flow of
FIG. 1
presents several obstacles to a designer seeking insight about the power dissipated by the design. Steps
10309
1035
, and
1040
are time consuming because they involve constructing layout information and simulating the design. A designer concerned about power dissipation may have to iterate through the loop indicated by steps
1020
,
1030
,
1035
,
1040
, and
1050
several times to obtain an acceptable result. This can substantially delay the development of a chip. Alternatively, because of the perceived development delay, the designer may be forced to proceed with a design that may not necessarily meet the specified power budget or that may dissipate power unnecessarily.
A power estimation method that doesn't rely on layout information and that doesn't require input stimuli to be simulated would allow designers to more easily understand and manage their power problems earlier in the design flow and in a more cost-effective manner. This is similar to problems in the timing of digital designs. Until recently, designers usually simulated their designs to understand if there were any timing problems in the design. In the last several years, however, static timing analysis has been adopted by many digital designers as a fast and accurate replacement for timing simulation. Static timing analysis predicts the timing problems in a design without performing any dynamic simulation of the design.
Several journal articles and conference papers have described methods of performing a similar static power analysis to estimate the dynamic power of combinational designs. These include the following which are hereby incorporated by reference:
1) Estimating Power Dissipation in VLSI Circuits by F. Najm, IEEE Circuits and Devices Magazine, Vol 10, Issue 4, pp. 11-19, July, 1994.
2) Estimation of Average Switching Activity in Comb
Khouja Adel
Krishnamoorthy Shankar
Mailhot Frederic G.
Meier Stephen F.
Siek Vuthe
Smith Matthew
Synopsys Inc.
Wagner , Murabito & Hao LLP
LandOfFree
Method and apparatus for estimating internal power... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for estimating internal power..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for estimating internal power... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2942568