Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-10-04
2005-10-04
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06952814
ABSTRACT:
A method and apparatus is provided by which a die designer can efficiently evaluate package routings associated with a die connection bump layout of a die. The die designer is equipped to determine appropriate placement of die connection bumps around a periphery of the die, designate signal and power assignments for die connection bumps, and check routings between die connection bumps and associated package pins. The die designer can efficiently iterate, without recourse to a package designer, through numerous die connection bump placement and assignment configurations to develop a die connection bump layout that is routable within a package. Thus, time required for iteration between the die designer and the package designer to establish a proper placement and assignment of die connection bumps is substantially reduced. Also, as design variables and constraints change during a die design process, the die designer can efficiently re-evaluate a die-to-package interface without recourse to the package designer.
REFERENCES:
patent: 5041903 (1991-08-01), Millerick et al.
patent: 5747874 (1998-05-01), Seki et al.
patent: 6225143 (2001-05-01), Rao et al.
patent: 6734046 (2004-05-01), Dahl
Joseph Matthew M.
Qin Zuxu
Lin Sun James
Martine & Penilla & Gencarella LLP
Smith Matthew
Sun Microsystems Inc.
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