Method and apparatus for error mitigation of programmable...

Details Method and apparatus for error mitigation of programmable... Method and apparatus for error mitigation of programmable...

2007-11-20

2007-11-20

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Reliability

Redundant

C326S009000, C326S011000

Reexamination Certificate

active

11787813

ABSTRACT:
A method and apparatus to reduce the probability of programmable logic device (PLD) failure due to single event upset (SEU) of configuration memory. A first portion of configuration memory cells are initially programmed with configuration data, leaving a second portion of configuration memory cells that are un-programmed. The programmed and un-programmed configuration memory cells are grouped into voting groups, where each un-programmed configuration memory cell of each voting group is programmed with the identical configuration data as contained within the originally programmed configuration memory cell of each voting group. The logic values of each configuration memory cell of each voting group are monitored by voting circuits, which enforce a triple modular redundancy (TMR) validation policy. The logical validation results are then applied to control points to mitigate PLD configuration memory errors caused by anomalous events such as neutron induced SEUs.

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U.S. Appl. No. 11/184,376 by Trimberger on Jul. 19, 2005 filed by Xilinx, Inc.
U.S. Appl. No. 11/184,498 by Trimberger on Jul. 19, 2005 filed by Xilinx, Inc.

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