Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-09-08
2004-02-24
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
06697989
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an error correction method using an apparatus for correcting errors in received information data and the error correction apparatus. More particularly, it relates to an error correction method and an error correction apparatus for correcting errors in information data to which error-correcting codes comprising a product code having inner codes and outer codes are added.
BACKGROUND OF THE INVENTION
Initially, a prior art error correction apparatus is described.
FIG. 9
is a block diagram illustrating a structure of the prior art error correction apparatus
50
.
The error correction apparatus
50
has a format interface
10
for executing demodulation processing for serial data
100
from an optical disk playback apparatus
6
and outputting demodulated data, a buffer memory
32
containing the demodulated data, an error correction circuit
20
for executing decoding including syndrome operation for the error-correcting codes, using the demodulated data from the format interface
10
or buffer memory
32
, a buffer memory manager
31
for controlling writing of the demodulated data onto the buffer memory
32
and reading of the demodulated data out of the buffer memory
32
, a descrambling circuit
33
for executing descrambling processing for demodulated data
300
which are read out of the buffer memory
32
, a data transfer circuit
34
for transferring data
301
from the descrambling circuit
33
after being subjected to the descrambling processing to an external apparatus as transfer data
302
, and a microcontroller
40
for outputting control signals to the respective circuits in the error correction apparatus
50
to control the whole operation of the error correction apparatus
50
.
The format interface
10
has a Sync code detection and removal circuit
11
for converting the received serial data
100
in parallel, to detect frame Sync codes, synchronizing the received data, and then removing the frame Sync codes, and a demodulation circuit
12
for executing the demodulation processing for information data
102
from the Sync code detection and removal circuit
11
.
The error correction circuit
20
has a first syndrome operation circuit
21
for executing syndrome operation for the demodulated data
106
from the demodulation circuit
12
, a second syndrome operation circuit
22
for executing syndrome operation for the demodulated data from the buffer memory
32
, a syndrome selection circuit
23
for selecting the syndrome operation result of one of the first and second syndrome operation circuits
21
and
22
and outputting the selected result, a Eucledean algorithm operation circuit
24
for deriving an error location polynomial and an error value polynomial on the basis of the syndrome operation result
202
from the syndrome selection circuit
23
, a chain search circuit
25
for calculating an error location from the degree of the error location polynomial, an error value operation circuit
26
for calculating an error value from the degree of the error value polynomial, an address generation circuit
27
for converting the calculated error location into a logical address
206
on the buffer memory
32
, and an error correction circuit
28
for reading data
207
at the logical address
206
which is output by the address generation circuit
27
and executing error correction.
That is, the error correction apparatus
50
judges whether errors are included in the received data on the basis of the operation result of the syndrome operation which is executed for the demodulated data, and judges whether the errors included in the received data are correctable errors on the basis of the degree of the error location polynomial which is derived from the syndrome operation result. When the errors included in the received data are correctable, the error location and error value are respectively obtained from the derived error location polynomial and error value polynomial, thereby to correct the errors in the received data.
In addition, the error correction apparatus
50
is constructed so that the demodulation of the received data and the decoding of the demodulated data is executed in the same order as the order in which the received data are received. Here, the description is given assuming that the error correction of inner codes is initially executed.
Next, prior art error correction processing is described with reference to a flowchart of FIG.
8
.
Initially in STEP
10
, when the serial data
100
(referred to also as received data) are input to the error correction apparatus
50
, synchronization of the received data is protected by the Sync code detection and removal circuit
11
. Then, in parallel with the demodulation processing in the demodulation circuit
12
, the syndrome operation is executed for the demodulated data
106
from the demodulation circuit
12
by the first syndrome operation circuit
21
.
In STEP
13
, it is judged whether a code length of data has been processed. When it is in the middle of the processing, the processing branches to LOOP
10
and the syndrome operation is continued. For example, in the case of the inner code of DVD as shown in
FIG. 6
, the code length of the received data is 182 bytes. When the processing for the code length of the data is completed, the processing proceeds to STEP
20
.
In STEP
20
, it is judged by the Eucledean algorithm operation circuit
24
whether there are errors in the received data on the basis of whether the result
200
of the syndrome operation from the first syndrome operation circuit
21
is zero. When the operation result
200
is zero, no error is included in the data and therefore the error correction processing is terminated.
When errors are included in the data, the processing proceeds to STEP
21
. In STEP
21
, the error value polynomial and the error location polynomial are derived by the Eucledean algorithm operation circuit
24
.
In the following STEP
22
, it is initially judged whether the errors included in the received data are capable of error correction on the basis of the degree of the error location polynomial (which indicates the number of the errors).
In the case of the inner code of DVD, 10 bytes of parity data are added and it has a 5-byte error correction capability. When this error correction capability is exceeded, the error correction is incapable. Therefore, the error correction processing of the inner codes is terminated.
When the errors included in the received data are capable of error correction, the processing proceeds to the following STEP
23
. In STEP
23
, the error location
204
is obtained from the coefficients of the error location polynomial by the chain search circuit
25
. This error location
204
is converted into the logical address
206
on the buffer memory
32
by the address generation circuit
27
and stored in the buffer memory
32
, and then the processing proceeds to STEP
24
.
In STEP
24
, the error value
205
is obtained from the coefficients of the error value polynomial by the error value operation circuit
26
as well as the logical address
206
of the error location, which is obtained in the previous STEP
23
, is read out of the buffer memory
32
. The error correction is executed for the read data
207
on the basis of the error value
205
.
In the next STEP
25
, when the degree of the error correction has been completed, the error correction processing of the inner codes is terminated. When it is in the middle of the error correction processing, the processing proceeds to LOOP
21
and the error correction for the remaining errors is continued.
Thus, in the prior art error correction method, the error location polynomial is obtained and the judgement as to whether errors included in the received data are capable of error correction can be made only on the basis of the degree of the obtained polynomial.
The erasure correction of the outer codes is executed when the degree of the error location polynomial derived by the Eucledean algorithm operation circuit
24
exceed
Iijima Yukio
Maeda Toshinori
De'cady Albert
Dooley Matthew C.
Matsushita Electric - Industrial Co., Ltd.
Wenderoth , Lind & Ponack, L.L.P.
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