Method and apparatus for entry of timing constraints

Details Method and apparatus for entry of timing constraints Method and apparatus for entry of timing constraints

1998-06-08

2000-12-26

Lintz, Paul R.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

716 8, 716 10, 716 6, 717 10, 703 23, G06F 1750

Patent

active

06167561&

ABSTRACT:
A method and apparatus providing a graphical user interface (GUI) that automatically determines timing groups and path groups for a circuit representation. In a first GUI display level, the GUI displays each path group in the circuit and allows the user to change the timing constraints for each path group. In addition, the GUI indicates whether each timing group is activated by a rising or falling clock signal. In addition, the user can define subpaths of a path group. After timing analysis software has analyzed the circuit, by clicking on a timing group in the first GUI display level, the user can view a second GUI display level, which shows details of the paths in the indicated timing group. By clicking on a path in the second GUI display level, the user can view a third GUI display level, which shows a list of each of the elements in the indicated path.

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Article by Steven E. Schulz entitled "Timing Verification Algorithms for Digital Designs," Design Automation, Mar. 1991, pp. 20-27.
Manual Pages, Group-Path Command Design Compiler, Version 1998.02, Publication Date: Unknown.
Manual Pages, Report-Timing Command Design Compiler, Version 1998.02, Publication Date: Unknown.

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