Method and apparatus for entering a low-power mode and controlli

Details Method and apparatus for entering a low-power mode and controlli Method and apparatus for entering a low-power mode and controlli

1993-09-27

1995-11-28

Harvey, Jack B.

395550, 395280, G06F 132, G06F 1300

Patent

active

054716250

ABSTRACT:
A method and apparatus for placing a data processor (12) into a low-power mode of operation using a system (10). The system (10) has a processor (12). The processor (12) has access to a bus (18). The bus (18) is coupled to a bus controller (14). The processor (12) sends a broadcast cycle out through the bus (18) when the processor (12) desires to enter a low-power mode of operation. The bus controller (14) determines that the broadcast cycle has been sent on the bus (18). The bus controller (14) waits a predetermined amount of time to process the low-power request and grants permission to the processor (12) to enter the low-power mode via the communication of a transmission termination signal. The processor (12) conditionally drives either logic ones or a tri-state value onto the bus (18) depending upon whether or not the processor (12) has been granted ownership of the bus (18).

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