Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
1999-02-19
2002-02-05
Shin, Christopher B. (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S040000, C710S107000, C710S124000, C710S244000, C710S120000, C709S232000
Reexamination Certificate
active
06345325
ABSTRACT:
FIELD OF INVENTION
The subject of the present invention in general pertains to a new Input-Output facility design that exploits high bandwidth integrated network adapters.
BACKGROUND OF THE INVENTION
In a network computing environment, multitudes of commands and requests for retrieval and storage of data are processed every second. To properly address the complexity of routing these commands and requests, environments with servers have traditionally offered integrated network connectivity to allow direct attachments of clients such as Local Area Networks (LANs). Given the size of most servers, the number of clients usually is in the range of hundreds to thousands and the bandwidth required in the 10-100 Mbits/sec range. However, in recent years the servers have grown and the amount of data they are required to handle has grown with them. As a result, the existing I/O architectures need to be modified to support this order of magnitude increase in the bandwidth.
In addition, new Internet applications have increased the demand for improved latency. The adapters must support a larger number of users and connections to consolidate the network interfaces which are visible externally. The combination of all the above requirements presents a unique challenge to server I/O subsystems.
Furthermore, in large environments such as International Business Machines Enterprise System Architecture/390 (Enterprise System Architecture/390 is a registered trademark of International Business Machines Corporation), there are additional requirements that the I/O subsystem must remain consistent with existing support. Applications must continue to run unmodified, and error recovery and dynamic configuration must be preserved or even improved. Sharing of I/O resources must be enabled as well as the integrity of the data being sent or received. This presents new and complex challenges that need to be resolved.
In order to achieve bandwidths which are dramatically higher and still achieve other required challenges, a new system architecture is needed.
This application is related to the following copending applications: PO9-99-013, Ser. No. 09/253,246; PO9-99-014, Ser. No. 09/253,250; PO9-99-015, Ser. No. 09/253,247; PO9-99-016, Ser. No. 09/253,248; PO9-99-017, Ser. No. 09/252,712; PO9-99-018, Ser. No. 09/252,552; PO9-99-019, Ser. No. 09/252,728; PO9-99-021, Ser. No. 09/253,101; PO9-99-022, Ser. No. 09/253,286; PO9-99-023, Ser. No. 09/252,542; PO9-99-024, Ser. No. 09/253,249; PO9-99-025, Ser. No. 09/252,556; PO9-99-026, Ser. No. 09/253,993; PO9-99-027, Ser. No. 09/253,658; PO9-99-028, Ser. No. 09/252,555; PO9-99-029, Ser. No. 09/255,641; PO9-99-030, Ser. No. 09/255,640; and PO9-99-031, Ser. No. 09/252,727.
SUMMARY OF THE INVENTION
A method and an apparatus for timely and accurate processing of data in a network computing environment controlled by a running program and having a queuing mechanism established in a main storage. The main storage is in processing communication with an interface element having one or more adapters. At least one set of queues in the queuing mechanism is designated for input and another set for output. A signal adapter instruction can be issued to provide initiative to check content of any or all queues in the mechanism. With the help of the signal adapter an initiate-output can be specified when appropriate and the associated adapter can then asynchronously process the input or the output queues. A synchronize option is also available to signal the associated data queues to update all entries in order to render them current as observed by both the adapter and the controlling running program.
REFERENCES:
patent: 4271468 (1981-06-01), Christensen et al.
patent: 5109489 (1992-04-01), Umeno et al.
patent: 5659794 (1997-08-01), Caldarale et al.
patent: 5784647 (1998-07-01), Sugimoto
patent: 5875343 (1999-02-01), Binford et al.
patent: 6052375 (2000-04-01), Bass et al.
patent: 6101533 (2000-08-01), Brandt et al.
Baskey Michael E.
Brice, Jr. Frank W.
Casper Daniel F.
Easton Janet R.
Glassen Steven G.
Gonzalez Floyd A.
Neff Lily
Shin Christopher B.
LandOfFree
Method and apparatus for ensuring accurate and timely... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for ensuring accurate and timely..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for ensuring accurate and timely... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2941479