Method and apparatus for enhancing the speed of a...

Details Method and apparatus for enhancing the speed of a... Method and apparatus for enhancing the speed of a...

2006-11-28

2006-11-28

Du, Thuan (Department: 2116)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S400000, C713S503000

Reexamination Certificate

active

07143304

ABSTRACT:
An apparatus for enhancing the speed of a synchronous bus includes a two register based FIFO with software control bits and a second clock signal. According to the invention, the second clock signal rd_clk is supplied by the same PLL that provides the main clock signal lg_clk. According to the invention, data is taken from the two registers in alternative clock cycles so that each of the register holds valid data for two clock cycles. A first software data bit is used to determine which of the two registers is unloaded first. Using the method and structure of the invention, the window for transferring valid data is increased and therefore the system employing the method and apparatus of the invention is more skew tolerant.

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