Method and apparatus for enhancing the performance of semiconduc

Details Method and apparatus for enhancing the performance of semiconduc Method and apparatus for enhancing the performance of semiconduc

1999-12-06

2000-10-03

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Differential sensing

365205, 365210, G11C 702

Patent

active

061282375

ABSTRACT:
A method and apparatus for reducing a peak current produced by the simultaneous activation of numerous sense amplifiers associated with an active word line, without reducing the speed of operation of the semiconductor memory device. A memory array includes word lines accessing memory cells and a tracking word line for sequentially activating the sense amplifiers connected to the digit lines by introducing a delay after the activation of each sense amplifier or group of sense amplifiers and before activating the next sense amplifier or group of sense amplifiers, so that the total time for activation of the sense amplifiers for all digit lines associated with an active word line is spread out, but is not longer than the time necessary for activation of an entire word line.

REFERENCES:
patent: 4926382 (1990-05-01), Sakui et al.
Daeje Chin et al., "An Experimental 16Mb DRAM with Reduced Peak-Current Noise," Samsung Electronics Co., Ltd., Semiconductor Business R&D Center, Kyungki-do, Korea.

Affiliated with

Also associated with

Rating

Method and apparatus for enhancing the performance of semiconduc does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for enhancing the performance of semiconduc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for enhancing the performance of semiconduc will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-201937