Method and apparatus for enhancing the performance of event...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07039887

ABSTRACT:
Disclosed is a full-chip level verification methodology that combines static timing analysis techniques with dynamic event-driven simulation. The specification discloses a capability to partition a multiple-clock design into various clock domains and surrounding asynchronous regions automatically and to determine the timing of the design on an instance by instance basis. Static timing analysis techniques can be leveraged to verify the synchronous cores of each clock domain. The asynchronous regions of the design and the interaction between synchronous cores of the clock domains are validated using detailed dynamic event-driven simulation without the burden of carrying the interior timing attributes of the synchronous cores that have already been verified.

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patent: 2002/0147555 (2002-10-01), Nagata et al.
Marschner, Erich et al., “Fast, Thorough, Full-Chip Implementation Verification”, Same 2000, Oct. 25, 2000, pp. 1-6.

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