Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2000-03-08
2001-12-04
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S121000, C326S027000
Reexamination Certificate
active
06326814
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to digital integrated circuits, and more particularly to dynamic logic circuits implemented in Silicon-On-Insulator (SOI) technology with enhancements that improve noise tolerance by reducing bipolar current effects and charge sharing effects within the circuits.
2. Description of the Related Art
Dynamic logic is widely used in integrated circuits, especially Very Large Scale Integrated (VLSI) circuits. Because dynamic logic uses comparably less transistors per gate than static logic, circuit densities are increased, making dynamic logic desirable for use in VLSI circuits such as microprocessors and memories.
Specifically, Complementary Metal Oxide Semiconductor (CMOS) technology has been the technology of choice for low power designs, because the bulk of the power dissipation in these circuits occurs when the transistors are switching. This characteristic has made CMOS implementations preferable for low power static designs, such as microprocessors and other components for use in notebook computers, and recently for desktops in keeping with the trend in “green” desktop computer design. CMOS technology uses P-channel and N-channel MOS devices in a static complementary configuration to form logic gates.
Dynamic gates are not typically complementary designs, as the P-channel devices and the N-channel devices are used to perform different functions in the gate. One transistor type is used to pre-charge an evaluation node, and the complementary type is use to discharge the node in response to logic inputs.
Silicon-On-Insulator (SOI) technology is a relatively new technology having enhanced low power characteristics, which make it ideal for implementing low power dynamic gates. Additionally, parasitic substrate capacitance is decreased, enhancing the switching speed of transistors implemented in SOI. Rather than embedding the channel material in a semiconductor substrate, the channel material is formed on top of an oxide layer, decreasing leakage resistance and parasitic capacitance. Devices are isolated by Shallow Trench Insulation (STI), rather than the substrate, further reducing capacitive effects and noise coupling from other devices.
There is a drawback associated with transistors formed in SOI technology, however. A parasitic bipolar transistor exists in both non-insulated MOS implementations and the SOI implementation. The bipolar transistor has an emitter and collector formed by the doped regions at the two ends of the channel (N+ material for an N-channel MOS transistor). The base of the transistor is formed by the substrate. In non-insulated MOS technology, the substrate is typically biased so that the transistor will always be off. For N-channel material, this bias is accomplished by connecting the substrate to the lowest negative potential in the circuit. In SOI implementations, because the channel material is deposited on an insulator, the base of the parasitic bipolar transistor (formed by the body of the MOS transistor) has no electrical connection. Therefore, when the doped material at the ends of the channel change voltage, the parasitic transistor may turn on until its base capacitance is charged. The conduction is produced by the forward bias of the emitter or collector (formed by the end of the channel) to the base (formed by the un-doped region in the middle of the channel). This is known as the “bipolar effect”, and can cause malfunction of dynamic gates implemented in SOI technology. The bipolar effect can cause glitches that discharge the evaluation node when the input state of a transistor coupled to that node changes in such a way that the parasitic bipolar transistor conducts momentarily.
Charge sharing is a problem common to both non-insulated MOS implementations and SOI implementations. When two or more transistors are connected in a chain so that both must conduct to discharge the summing node of a dynamic logic gate, if a device farther away from the summing node is in a non-conducting state and a device closer to the summing node is enabled, the preset voltage on the summing node can be dissipated due to charging the diffusion capacitance of the farther device.
The bipolar effect and the charge sharing effect decrease the noise immunity of a dynamic logic gate, as well as increasing the sensitivity to coupling from other input signals and sub-threshold variations in voltages at the gate's logic inputs.
It would therefore be desirable to implement dynamic logic circuits in such a way that the bipolar effect and charge sharing effect can be reduced or eliminated.
SUMMARY OF THE INVENTION
The objective of enhancing noise immunity in Silicon-On-Insulator (SOI) dynamic logic gates is accomplished in a dynamic logic gate that includes a pre-charge transistor, one or more logic ladders having multiple logic inputs and a pull-up ladder for holding a summing node at a pre-charge state. The pull-up ladder has multiple transistors and the gates of the transistors are each coupled to a unique logic input. The logic ladder and pull-up ladder are both coupled to the summing node of the logic gate.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 6052008 (2000-04-01), Chu et al.
patent: 6133759 (2000-10-01), Beck et al.
patent: 6150869 (2000-11-01), Storino et al.
patent: 6163173 (2000-12-01), Storino et al.
Davies Andrew Douglas
Stasiak Daniel Lawrence
Bracewell & Patterson
International Business Machines - Corporation
Le Don Phu
Tokar Michael
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