Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-08-23
2005-08-23
Bonzo, Bryce P. (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S044000, C714S056000
Reexamination Certificate
active
06934888
ABSTRACT:
A method, apparatus, and computer instructions for processing errors in a hierarchical hardware sub-system in the data processing system in which the hierarchical hardware sub-system includes a host processor bridge having a mapping registers section and a control and status registers section. In response to detecting an error freezing the mapping registers section in the host bridge, a component within the hierarchical hardware sub-system connected to the host bridge is identified to form a selected component. An address is written to a register within the control and status registers section of the host bridge in which the address is to an error register in the component. Data is read in response to a result from the address written in the register being placed in the control and status registers portion of the host bridge.
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Mai-Simpson Sophia
McIntosh Gordon D.
Bonzo Bryce P.
Maskulinski Michael
Yee Duke W.
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