Method and apparatus for enhanced CMP planarization using...

Details Method and apparatus for enhanced CMP planarization using... Method and apparatus for enhanced CMP planarization using...

2007-06-26

2007-06-26

Estrada, Michelle (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C716S030000, C257SE21151

Reexamination Certificate

active

11181433

ABSTRACT:
In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.

REFERENCES:
patent: 5441915 (1995-08-01), Lee
patent: 5790417 (1998-08-01), Chao et al.
patent: 5798298 (1998-08-01), Yang et al.
patent: 5926733 (1999-07-01), Heo
patent: 6448630 (2002-09-01), Komori
Brian Lee et al., “Using Smart Dummy Fill and Selective Reverse Etchback for Pettern Density Equalization”, Proc. CMP-MIC, pp. 255-258, Santa Clara, CA, Mar. 2000.

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