Method and apparatus for encoding valid and invalid states in a

Details Method and apparatus for encoding valid and invalid states in a Method and apparatus for encoding valid and invalid states in a

1997-11-26

2000-03-28

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711145, 711154, 711156, 711 3, G06F 1200

Patent

active

06044441&

ABSTRACT:
A cache controller unit includes an address comparator unit for comparing an address to be accessed in memory with a tag address. An invalid pattern comparator is coupled to the address comparator. The invalid pattern comparator operates to compare the tag address with an invalid pattern. A qualifier unit is coupled to the address comparator and the invalid pattern comparator. The qualifier unit outputs a signal when the address to be accessed in the memory matches the tag address in the address tag and the address tag does not match the invalid pattern.

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patent: 5960456 (1999-09-01), Herbst

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