Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-01-16
2007-01-16
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S774000
Reexamination Certificate
active
10874611
ABSTRACT:
A method for interlacing columns of different weights is proposed for a parity-check matrix H that results in good performing LDPC codes shortened or unshortened. Matrix H comprises a section H1and a section H2, and wherein H1has a plurality of different column weights and comprises a plurality of sub-matrices where columns of at least one weight are substantially interlaced between the sub-matrices.
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Blankenship Yufei
Classon Brian K.
Baker Stephen M.
Haas Kenneth A.
Motorola Inc.
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