Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-01-30
2007-01-30
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S799000, C714S800000, C714S801000
Reexamination Certificate
active
10839995
ABSTRACT:
A deterministic structure for controlled distribution of weight-2 columns is proposed for a parity-check matrix H that reduces the occurrence of undetected frame errors and significantly enhances the code performance in comparison to a randomly-constructed parity-check matrix. H comprises a non-deterministic section H1and a deterministic section H2, and wherein H2comprises a first part comprising a column h having an odd weight greater than 2, and a second part comprising matrix elements for row i, column j equal to1 for i=j,1 for i=j+1,0 elsewhere.
REFERENCES:
patent: 2004/0098659 (2004-05-01), Bjerke et al.
Blankenship Yufei W.
Classon Brian K.
Desai Vipul A.
Dildine R. Stephen
Motorola Inc.
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