Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2008-03-11
2008-03-11
Lamarre, Guy J. (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C714S752000, C714S758000
Reexamination Certificate
active
07343548
ABSTRACT:
A structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix Hb. Base matrix Hbcomprises a section Hb1and a section Hb2. Section Hb2comprises column hbhaving weight wh>=3 and H′b2having a dual-diagonal structure with matrix elements at row i, column j equal to 1 for i=j, 1 for i=j+1, and 0 elsewhere. The 1's of hband Hb1are arranged such that one or more groups of the rows of Hbcan be formed so that the rows of Hbwithin each group do not intersect. Further more, the rows of base matrix Hbcan be permuted such that every two consecutive rows do not intersect.
REFERENCES:
patent: 6718508 (2004-04-01), Lodge et al.
patent: 7188297 (2007-03-01), Blankenship et al.
patent: 7260763 (2007-08-01), Sukhobok et al.
patent: 2004/102810 (2004-11-01), None
Blankenship T. Keith
Blankenship Yufei W.
Classon Brian K.
Lamarre Guy J.
Motorola Inc.
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