Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-02-06
2009-02-17
Lamarre, Guy J (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S801000, C714S786000, C714S755000
Reexamination Certificate
active
07493548
ABSTRACT:
A structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix Hband wherein Hbcomprises a section Hb1and a section Hb2, and wherein Hb2comprises a first part comprising a column hbhaving an odd weight greater than 2, and a second part comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, and 0 elsewhere. The expansion of the base matrix Hbuses identical submatrices for 1s in each column of the second part H′b2, and the expansion uses paired submatrices for an even number of 1s in hb.
REFERENCES:
patent: 5956351 (1999-09-01), Bossen et al.
patent: 7464323 (2008-12-01), Piret et al.
patent: 2004/0221223 (2004-11-01), Yu et al.
patent: 2005/0246617 (2005-11-01), Kyung et al.
patent: 2005/0257119 (2005-11-01), Blankenship et al.
Blankenship Yufei
Classon Brian
Nimbalker Ajit
Lamarre Guy J
Motorola Inc
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