Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-10-06
2001-05-22
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06237128
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to the field of computer system design and test management. More particularly, it relates to a method for designing VLSI (Very Large Scale Integrated)-chips.
FIELD OF THE INVENTION
VLSI circuit design requires thousands of circuits and components to be physically placed and connected on a chip. This can be very costly, especially given that the actual process of designing, placing, and connecting the circuits on the chip can affect the performance and timing thereof. Therefore, it has become necessary to automate the design process to quickly place and wire predesigned circuits into a functional chip.
BACKGROUND OF THE PRIOR ART
In VLSI physical design, there exist two different concepts, the Hierarchical Design and the Flat Design. The hierarchical approach is described in EP-B-0 271 596 to Pollmann et al. The circuit to be placed on-chip is logically partitioned into a number of functional subunits and each logical subunit is accommodated on a (rectangular) physical partition of chip area. Each of the logical partitions is manageable by the automatic design systems and programs presently known. Thus, the chip is composed of large logical components. These logical components are either built by standard physical design methods or custom designs. This design process is used when the physical design programs can not handle the full chip's netlist in placement and wiring or custom design can not be handled for the full chip, respectively. Each unit can be layout checked standalone and the full chip can be checked using black boxes as representers of these units. The disadvantages of this approach are that the components have to be built and verified rather a long time before the chip release. Furthermore, as the components are physical units for themselves, optimal placement and wiring of circuits contained in pathes crossing these units is not possible.
In U.S. Pat. No. 5,218,551, it is described how parts of the total chip design are assigned to precincts of the chip space. Next, basic elements are interchanged between said precincts in order to optimize chip overall timing and wirability.
In the flat design approach (see J. Koehl et al., “A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset”, to appear in Proc. of DATE 1998) physical design methods enable the placement of any circuit on any place of the entire chip (except for some blockages) leading to optimal placement and wiring. Here, the chip space is not segmented at all. One advantage of this method is that the logical netlist can be changed relatively late prior to physical design. However, the chip, as a whole, can not be checked with respect to logic versus physical checking (LVS) and design rules check (DRC) restrictions of the checking equipment. In addition, the layout verification tools consume too much memory and CPU time resulting in a too high checking turn around time.
Currently, there are also three approaches in reducing the ressources needed for layout verification. Using hierarchical verification, the layout is checked bottom up. This requires the early design of the hierarchical units and the verification of the layout as well as of the representers needed.
In parallel checking, checking decks are split into several jobs each containing a group of checks on distinct related layers. While this reduces run time, it does not reduce peak memory requirements.
A solution of this problem would be the partitioning of the layout for checking only (physical partitioning, windowing). While this reduces peak memory, one must create an overhead to generate representers of the neigbour regions to avoid missing real errors or getting pseudo errors. However, this approach requires much manual intervention and is therefore time consuming. Also, this method only applies for DRC, not for LVS.
SUMMARY OF THE INVENTION
To reduce the storage requirements for and to enable DRC and LVS checking, future chips need to be partitioned. In this context, “enable” means to keep the main storage requirements below layout checking tools' limits and to shorten the checking cycle through parallelism.
Thus, it is an object of the present invention to provide a method for designing VLSI-chips that enables LVS and DRC checking to be used for chips carrying a huge number of circuits and components, while keeping the penalty for physical design to almost zero.
This and other objects are achieved by the present invention providing a method for designing VLSI chips comprising the steps of
a) partitioning the chip area into several segments,
b) providing physical decoupling of said segments by introducing divider macros at each boundary of said segments; and
c) placing circuitry on said segments, whereby the circuitry associated with each segment has a complexity that can be handled by available testing devices.
One decisive advantage of the present invention is the fact that future run time and data volume issues for DRC and LVS checking of large high density VLSI-chips can be resolved and kept below a certain limit by parallelising, i.e., checking the partitions parallel to each other, the verification as much as necessary, thereby retaining the flat design approach as well as the advantages of the hierarchical approach.
REFERENCES:
patent: 5046012 (1991-09-01), Morishita et al.
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5475583 (1995-12-01), Bock et al.
patent: 5705301 (1998-01-01), Garza et al.
patent: 5774371 (1998-06-01), Kawakami
patent: 5883814 (1999-03-01), Luk et al.
patent: 3-105972 (1991-05-01), None
Folberth Harald
Keinert Joachim
Koehl Jürgen
Pollmann Kurt
Rettig Oliver
Ehrlich Marc A.
Gonzalez Floyd A.
International Business Machines - Corporation
Siek Vuthe
Smith Matthew
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