Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2007-08-28
2007-08-28
Deppe, Betsy L. (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S156000
Reexamination Certificate
active
10680636
ABSTRACT:
In a method and apparatus for enabling fast clock phase locking in a phase-locked loop, a sampling clock generator generates sampling clock signals in response to an oscillator output of the phase-locked loop. A detector unit samples an input digital signal to the phase-locked loop at clock edges of the sampling clock signals to obtain multiple sampling points of the input digital signal, and compares logic levels of each temporally adjacent pair of the sampling points to detect presence of a logic level transition in the input digital signal. A selector unit is controlled by the detector unit to select one of the sampling clock signals, which has one of the clock edges thereof defining an interval that was detected to have occurrence of the logic level transition in the input digital signal, and which is subsequently provided to the phase-locked loop as an input phase-locking clock signal.
REFERENCES:
patent: 6442225 (2002-08-01), Huang
patent: 6583674 (2003-06-01), Melava et al.
patent: 6815987 (2004-11-01), Hsu et al.
patent: 2002/0090045 (2002-07-01), Hendrickson
Chen Chih-Cheng
Chen Jong-Woei
Hsu Tse-Hsiang
Liu Ding-Jen
Deppe Betsy L.
Mediatek Inc.
Thomas Kayden Horstemeyer & Risley
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