Method and apparatus for enabling cache streaming

Details Method and apparatus for enabling cache streaming Method and apparatus for enabling cache streaming

1997-03-28

1999-12-28

Chan, Eddie P.

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

711118, 710119, 710107, 710113, 710126, G06F 1200, G06F 1300

Patent

active

060094826

ABSTRACT:
A process and implementing computer system in which an arbitration circuit is comprised of a plurality of state machines 301, 303 and 305 which combine to receive various system timing signals and provide a data bus grant signal effective to enable data streaming of sequential data blocks of information from an L2 cache memory 109 without intervening wait states between the data blocks.

REFERENCES:
patent: 4853848 (1989-08-01), Mitsuhashi et al.
patent: 5537555 (1996-07-01), Landry et al.
patent: 5559968 (1996-09-01), Stancil et al.
patent: 5596729 (1997-01-01), Lester et al.
patent: 5781925 (1998-07-01), Larson et al.

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