Method and apparatus for employing a cycle bit parallel executin

Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word

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712 23, G06F 938

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061548286

ABSTRACT:
A method and apparatus including means for storing an executable file which includes a group of bits which define functional operations and cycle bits associated with each functional operation and means for completing a variable number of the functional operations in parallel during a single execution cycle in accordance with a state of the associated cycle bit. The method and apparatus eliminates the need for complex data dependency checking hardware and allows a minimum amount of control logic to complete execution of executable files. The method and apparatus further minimizes the necessity of adding null operations (NOPs) to executable files which reduces the amount of storage space necessary to store the executable files and allows executable files to be used on multiple hardware implementations and for register values to be used for multiple purposes during single execution cycles.

REFERENCES:
patent: 4829422 (1989-05-01), Morton et al.
patent: 4833599 (1989-05-01), Colwell et al.
patent: 5051940 (1991-09-01), Vassiliadis et al.
patent: 5073855 (1991-12-01), Staplin et al.
patent: 5185872 (1993-02-01), Arnold et al.
patent: 5197135 (1993-03-01), Eickemeyer et al.
patent: 5203002 (1993-04-01), Wetzel
patent: 5295249 (1994-03-01), Blaner et al.
patent: 5303356 (1994-04-01), Vassiliadis et al.
patent: 5337415 (1994-08-01), DeLano et al.
patent: 5355460 (1994-10-01), Eickemeyer et al.
patent: 5371862 (1994-12-01), Suzuki et al.
patent: 5398321 (1995-03-01), Jeremiah
patent: 5448746 (1995-09-01), Eickemeyer et al.
patent: 5465377 (1995-11-01), Blaner et al.
patent: 5502826 (1996-03-01), Vassiliadis et al.
patent: 5504732 (1996-04-01), Vassiliadis et al.
Acosta et al, an Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors, IEEE Trans. on Coup. vol. C-35, No. 9, Sep. 1986.
Kondoh et al, Parallel Processing of Finely Grained Tasks: Arbitrating Synchrounizer & Parallel Scheduler, Indust. Elect. Ctrl & Instrum., 1991 Intl. Conf. pp. 1425-1430.
Smith, Dynamic Instruction Scheduling and the Astronautics ZS-1, Computer Magazine, Jul. 1989, vol. 22 Issue 7 pp. 21-35.
Minagawa et al, Pre-Decoding Mechanism for Superscalar Architec. Communications, Computers & Signal Processing, 1991, pp. 21-24.
Smith, Dynamic Instruction Scheduling and the Astronautics ZS-1, IEEE Jul. 1989.
Torng et al, on Instruction Windowing for Fine--Grain Parallelism in High Performance Processors, IEEE Mar. 1993.
"A VLIW Architecture for a Trace Scheduling Compiler", by Robert P. Colwell, Robert P. Nix, John J. O'Donnell, David B. Papworth, Conference on Architectural Support for Programming Languages and Operating Systems, Published October 1987.

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