Method and apparatus for eliminating sampling errors on a...

Details Method and apparatus for eliminating sampling errors on a... Method and apparatus for eliminating sampling errors on a...

2005-03-10

2008-10-07

Elamin, Abdelmoniem (Department: 2116)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S375000, C713S400000, C375S354000, C375S355000, C375S360000

Reexamination Certificate

active

07434084

ABSTRACT:
A synchronous bit-serial data interface utilizes a transmitter that transmits a data stream having duplicates of each data bit. The receiver samples the data stream utilizing either the rising or falling edge of a received clock signal. If the rising edge is utilized the first duplicated bit is discarded and if the falling edge is utilized the second duplicated bit is discarded. The system allows transmitter/receiver pairs of devices that sample and latch data on the same clock edge to communicate.

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Agere Systems, Synchronous Bit-Serial Data Interface Timing, Application Note, May 21, 2004, Agere Systems Inc, Allentown, PA: <http://www.eetasia.com/ARTICLES/2004DEC/A/2004DEC16—ID—AN01.pdf>.

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