Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration
Reexamination Certificate
1999-04-20
2002-08-20
Thai, Xuan M. (Department: 2181)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
C710S002000, C710S008000, C710S300000, C710S104000
Reexamination Certificate
active
06438686
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention pertains to the field of computer systems. More particularly, the present invention pertains to avoiding contention of multiple devices on a bus.
2. Description of Related Art
Many bus masters in current computer systems are configured automatically by the computer system itself. For example, particular interrupt values and address ranges are typically assigned to peripheral devices, and these peripheral devices may not respond until accessed by the system. Such system self-configuration often avoids bus contention.
Nonetheless, some bus masters may expect to have control of a certain bus or a certain resource upon normal system initialization. As a result, bus contention may be caused if an additional bus master that also expects to have control of the same resource is added in a system to provide increased throughput or to otherwise upgrade the system. The capability to automatically disable one of two contending bus masters might advantageously simplify user upgrades and system manufacturer reconfigurations.
One prior art example of a bus master that may expect control of a system bus is a microprocessor. Some prior art systems allow a second microprocessor to be plugged in to an upgrade slot. In order to avoid contention between the two processors, this system continuously asserts an “upgrade present” signal to prevent the original processor from driving the bus. This approach requires a dedicated pin and a pre-defined special mode entered when the upgrade present signal is asserted.
Another example of a component that may expect to be a bus master without any initial configuration is an accelerated graphics port (A.G.P.) bus master. Typically, the A.G.P. bus is a two load bus, hosting an A.G.P. bus master and a bus controller. The bus controller may be a “north bridge” also coupled to the system processor and memory. Further details regarding the A.G.P. bus may be found in the Accelerated Graphics Port Specification, Version 2.0, May 4, 1998, which is available from the Accelerated Graphics Port Implementers Forum on the Internet at http://www.agpforum.org as of the time of filing of this application.
One prior art system includes a three load A.G.P. bus. In this system, an on-board A.G.P. bus master is provided on a computer system motherboard in addition to the north bridge. A connector that is coupled to the A.G.P. bus is also provided for adding an upgraded A.G.P. bus master on an add-in card. In order to perform an upgrade, however, a jumper block on the motherboard is used to manually disable the on-board A.G.P. master and to enable the add-in card master by routing the FRAME# signal only to the selected A.G.P. master.
Thus, the prior art may fail to provide an automatic software configurable design for a three load A.G.P. system. Such a system may be advantageous in simplifying user and reseller system reconfigurations. Moreover, the prior art may fail to provide a generalized system that avoids bus contention by disabling a default bus master to test for an alternate bus master and/or by sequencing through system reset more. than once
SUMMARY
A method and apparatus for eliminating contention with dual masters is disclosed. One method disclosed disables a default bus master, and tests for a second bus master. If the second bus master fails to respond, the default bus master is enabled.
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Daughtry Gregory M.
McRonald Andrew J.
Ramesh Srithar
Tran Hieu T.
Draeger Jeffrey S.
Intel Corporation
Thai Xuan M.
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