Method and apparatus for efficiently transferring data...

Details Method and apparatus for efficiently transferring data... Method and apparatus for efficiently transferring data...

1999-01-19

2002-07-30

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S209000, C711S105000

Reexamination Certificate

active

06427199

ABSTRACT:

FIELD OF THE INVENTION
This invention relates in general to selective call radios, and particularly, to a method and apparatus for efficiently transferring data between peripherals in a selective call radio.
BACKGROUND OF THE INVENTION
As demand for portable battery-operated units continues to grow, manufacturers of these portable units are striving to improve power efficiency to extend their battery life. Improvements in submicron semiconductors fabrication has significantly contributed to an extended battery life for portable units. However, there are circumstances where power efficiency remains below expectations.
This problem generally arises when peripherals of differing memory architectures are coupled together through a standard bus. For example, to update registers of an 8-bit peripheral coupled to a standard conventional 32 bit bus, such as the AMBA (Advanced Micro-controller Bus Architecture), a sourcing peripheral (e.g., a microprocessor) is forced to use the lower 8 bits of the data bus to execute read and write cycles to these registers. Table
1
of
FIG. 1
illustrates how registers of an 8-bit peripheral (e.g., a memory) are mapped both in memory space and on the data bus of an AMBA standard bus.
The first column of Table
1
provides the address mapping of registers “R
0
” through “R
7
”. The subsequent four columns of Table
1
show the bit range assignment of these registers on the AMBA data bus. As should be evident from Table
1
, register “RO” is memory mapped so that it occupies addresses 0 through 3 in hex. For performing read and write cycles, only the lower 8 bits of the 32 bit data bus (i.e., D[
7
:
0
]) are utilized. The upper 24 bits of the 32 bit data bus (i.e., D[
31
:
8
]) are kept either floating or fixed to a particular logic value (e.g., “
0
”) during a read or write cycle. Hence, in the instance where registers “RO” through “R
7
” need to be updated, eight 32 bit write cycles are necessary to complete the update of these registers. Clearly, each of these write cycles fails to take advantage of the upper three unused bytes (i.e., D[
31
:
24
], D[
23
:
16
]) and D[
15
:
8
]) of the 32 bit data bus, which if utilized could reduce the foregoing update to two write cycles, thereby substantially reducing power consumption.
To avoid the foregoing problem, prior art systems have concatenated 8 bit registers to utilize all byte positions of a 32 bit data bus. This method is illustrated in Table
2
as depicted in FIG.
2
. According to this method, registers “R
0
” through “R
3
” occupy the memory space 0 through 3 in hex. Each register occupies a corresponding byte segment of the data bus, thereby utilizing the entire bit range of the data bus. Hence, to update registers “R
0
” through “R
3
”, a 32 bit microprocessor will source a 32 bit write cycle, whereby “R
0
” occupies the most significant byte of the data bus (i.e., D[
31
:
24
]), “R
1
” occupies the next contiguous byte segment of the data bus (i.e., D[
23
:
16
]) and so on as shown in FIG.
2
. Consequently, only two write cycles (one at addresses “0”, and the other at address “4” in hex) are necessary for updating eight registers. This improves power efficiency by a factor of approximately 400% when compared to the previous example. Although on its face the improvement is substantial, this method in the art continues to suffer from inefficiencies in certain circumstances.
Principally, problems arise when in the example above only a few registers need to be updated. For example, assume that only registers “R
0
” and “R
4
” require an update. In this instance, the sourcing device must recall the values of “R
1
” through “R
3
”, and “R
5
” through “R
7
”, respectively, to avoid overwriting the values included in these registers. Because of the additional software instructions cycles necessary for retrieving information on the unchanged registers, the power savings originally mentioned are substantially diminished in circumstances where only a few concatenated registers need to be updated.
The impact that the aforementioned deficiencies in the prior art have on the battery life performance of portable battery operated units becomes evident when power efficiency is calculated over millions of data transactions occurring between peripherals included in a selective call radio. Accordingly, what is needed is a method and apparatus for efficiently transferring data between peripherals in a selective call radio.


REFERENCES:
patent: 3914747 (1975-10-01), Barnes et al.
patent: 5440755 (1995-08-01), Harwer et al.
patent: 5469003 (1995-11-01), Kean
patent: 5751975 (1998-05-01), Gillespie et al.

Affiliated with

Also associated with

Rating

Method and apparatus for efficiently transferring data... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for efficiently transferring data..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for efficiently transferring data... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2901214