Method and apparatus for efficiently testing rambus memory devic

Details Method and apparatus for efficiently testing rambus memory devic Method and apparatus for efficiently testing rambus memory devic

1999-07-06

2000-11-07

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

365200, 36518902, 36523002, G11C 1300, G11C 700

Patent

active

061445983

ABSTRACT:
A RAMBUS dynamic random access memory includes a test control circuit that selectively couples a row address latch to either a row sense control signal or a CMD control signal. In a normal operating mode, the test control circuit couples the row address latch to the row sense control signal so that the row sense control signal both latches a row address and senses a row of memory cells corresponding to the latched address. Prior to conducting a core noise test, the test control circuit couples the row address latch to the CMD control signal so that the row address is latched by the CMD control signal, and the row sense control signal only functions during the core noise test to sense a row corresponding to the latched row. The memory also includes a multiplexer that receives a time-multiplexed data/address bus and simultaneously couples a first part of the data/address bus to an internal data bus and a second part of the data/address bus to an internal address bus.

REFERENCES:
patent: 3845476 (1974-10-01), Boehm

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