Method and apparatus for efficiently implementing trace...

Details Method and apparatus for efficiently implementing trace... Method and apparatus for efficiently implementing trace...

2006-05-23

2006-05-23

Baderman, Scott (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S030000, C714S033000, C714S041000

Reexamination Certificate

active

07051239

ABSTRACT:
A system is disclosed in which an on-chip logic analyzer (OCLA) is included in an integrated circuit, such as a microprocessor. During debug modes, one or more sets of an on-chip cache memory are disabled from use by other circuitry in the integrated circuit, and reserved exclusively for use by the OCLA. Data stored in the reserved cache set can then be read out by the OCLA, and placed in a register that can be accessed by other logic internal or external to the integrated circuit. If the integrated circuit is operating under normal mode, the cache memory set can be used in conventional fashion by other circuitry with in the integrated circuit to enhance performance.

REFERENCES:
patent: 6618775 (2003-09-01), Davis
patent: 6704895 (2004-03-01), Swoboda et al.
patent: 6742145 (2004-05-01), Bailey et al.
patent: 6772369 (2004-08-01), Smith et al.

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