Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
2000-07-12
2004-05-25
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S039000, C710S040000, C710S052000, C710S053000, C710S071000, C710S307000, C710S310000, C710S313000, C710S315000
Reexamination Certificate
active
06742063
ABSTRACT:
BACKGROUND OF INVENTION
The present invention is related to the area of data transfer between units within or connected to a system for data processing, and, in particular, to a method and apparatus for efficient transfer of data in data processing systems comprising devices and other units with data buses which are operating at different speeds. More particularly the invention is related to a method and apparatus for efficient transfer of data packets or data organised in blocks between devices with low-speed interfaces that are interfaced to a high-performance central processing unit (CPU) system bus.
In modern data processing systems the need for rapidly transferring large amounts of data continues to increase, and new and fast growing technologies that make use of such data processing systems such as e.g. the Internet and digital telephony which have become available to the public has spurred a further growth in research and development in the field of low and moderate cost high-performance computers with enhanced capabilities. As the new high-performance CPU systems have become commonplace at low cost, one of the obstacles that have been met in taking on the challenges of this field is to efficiently make use of the abilities of new high-performance CPU systems to communicate by rapid data transfer. Such enhanced data transfer to and from the devices found in the environment of these high-performance CPU systems is needed to communicate further with networks, other peripheral devices and the like and to bridge the performance gaps that may exist between these units and devices.
In prior art data systems, interfacing of low-speed devices to high-performance CPU systems for improving the input/output (I/O) and data transfer have usually been accomplished by means of either interrupts, direct memory access (DMA) or a combination of the two. However, these methods suffer from problems related to the fact that the limitations of the low-speed devices still affect possibility for efficiently gaining access to and making full use of the higher speed CPU bus. Interrupt driven systems show low latency, but handling of interrupt routines is time consuming and will consequently put severe limitations on the up-scaling of such systems. The DMA driven systems are better in that respect, but the limitations of the low-speed device itself are still transparent to the high-speed CPU bus.
In addition to the above mentioned commonly employed interrupts and DMA means for improving data transfer in high-performance CPU systems, other means have been developed to address the problem of providing high-efficiency data transfers in various systems encountering higher needs for data throughput. In U.S. Pat. No. 5,862,128 to Cooperman et. al., a digital circuit switch is disclosed which, in order to solve a throughput problem at peak traffic conditions, makes use of a single merged buffer that is outside the circuit switch fabric to temporarily store correctly and incorrectly routed signals which subsequently are sent to the correct destination when the output port is no longer busy. The problem of interconnecting systems with different properties is addressed in U.S. Pat. No. 561,002 to Van Seters et. al. which discloses a device and a method for internetworking whereby a translation of data packet headers is accomplished in a process which involves separating the data packet header from the data packet itself. U.S. Pat. No. 5,764,895 to Chung, discloses a local area network (LAN) method and device for directing data packets in a LAN, wherein the disclosed LAN device has a plurality of ports interconnected by a high-speed communication bus. Finally, two Japan patent publications no.JP 9319680A and JP 11011387A disclose, respectively, an invention for improvement in utilisation of buffer memory by use of a single buffer memory for forwarding the same data to a number of processing units in a system which includes several processing units and an invention for prevention of transmission of excess data packets between a pair of data-processing systems by control of receiving buffers provided in the bus controllers in each of the systems. Although the above mentioned disclosures and prior art methods address different aspects of efficient data transfer and data throughput, the problem that still remains to be solved is that of providing new improvements in efficient interfacing of low-speed devices or devices that have different data transfer performance characteristics to a central processing unit (CPU) system bus such as a high-performance central processing unit (CPU) system bus for transferring of packet-oriented data in a data processing system.
BRIEF SUMMARY OF INVENTION
It is therefore an object of the present invention to provide a method whereby data packets can be transferred efficiently between devices provided with data transfer interfaces and a high-performance central processing unit (CPU) system bus in data processing systems in which the devices and the CPU bus have different data transfer performance characteristics.
It is a further object of the present invention to provide a device capable of efficiently transferring data packets between devices provided with data transfer interfaces and a high-performance central processing unit (CPU) system bus in data processing systems in which the devices and the CPU bus have different data transfer performance characteristics.
It is a further object of the invention to provide isolation between a low-speed device and a high-speed device, thus making the high-speed device insensitive to the interfaces of the low-speed device. At the same time data is packed and shipped in a format for optimal data transfer on the high-speed CPUs bus. Altogether, the high-speed CPU is loaded to a very low degree even though the interfaced devices are slow. Since the method is very well suited for instansiation it lends itself to scaling, and several low-speed devices may thus be added to a system without impairing the overall performance.
These and other objects of the present invention are accomplished by the method and the device according to the present invention disclosed herein and as set out in the accompanying patent claims.
The present invention is particularly suitable in situations where data is transferred in blocks. This is the case for e.g. devices interfacing to the Internet where data is packet oriented.
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Cypress homepage—“Build a FIFO ‘Dipstick’ With a CY7C371i CPLD”.
Cypress homepage—“Use a PLD and FIFOs to Convert Bus Width”.
Cypress homepage—“FIFO Dipstick Using Warp2® VHDL and the CY7C371”.
Cypress homepage—“Designing With CY7C436xx Synchronous FIFOs” Feb. 1999.
Texas Instruments “Interfacing TI Clocked FIFOs With TI Floating-Point Digital Signals Processors” Mar. 1996.
Hellum Pål Longva
Kleven Bjørn Kristian
Gaffin Jeffrey
Nixon & Vanderhye P.C.
Patel Niketa
Telefonaktiebolaget LM Ericsson (publ)
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