Method and apparatus for efficient implementation and...

Electronic digital logic circuitry – Multifunctional or programmable – Sequential or with flip-flop

Reexamination Certificate

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C704S232000, C706S020000, C700S048000

Reexamination Certificate

active

07119577

ABSTRACT:
A method and apparatus for efficient implementation and evaluation of state machines and programmable finite state automata is described. In one embodiment, a state machine architecture comprises a plurality of node elements, wherein each of the plurality of node elements represents a node of a control flow graph. The state machine architecture also comprises a plurality of interconnections to connect node elements, a plurality of state transition connectivity control logic to enable and disable connections within the plurality of interconnections to form the control flow graph with the plurality of node elements, and a plurality of state transition evaluation logic coupled to the interconnections and operable to evaluate input data against criteria, the plurality of state transition evaluation logic to control one or more state transitions between node elements in the control flow graph.

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