Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2001-07-13
2002-10-29
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S116000, C710S305000, C710S240000
Reexamination Certificate
active
06473817
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to computers. More particularly, the invention relates to bus arbitration within a computer.
2. Description of the Related Art
FIG. 1
is a block diagram showing a computer system
10
. The computer system
10
includes a processor bus
12
coupled to a cache memory
14
and to a computer processor
16
. Typical processor buses currently operate at clock speeds between 66 MHz and 133 MHz. The computer system
10
also includes a system memory
17
coupled to the processor bus
12
by a memory controller
18
. A Peripheral Components Interconnect (PCI) bus
22
is also coupled to the processor bus
12
by a PC-host bridge
20
. The PCI bus
22
is used to separate the operation of the peripheral components from the functions executed over the processor bus
12
so that the processor bus
12
may remain dedicated to directly serving the computer processor
16
. Separating these operations increases the effective operation speed of the computer. Typical PCI buses currently operate at clock speeds between 33 MHz and 66 MHz. A graphics monitor
26
is coupled to the PCI bus
22
by a graphics controller
24
. An Industry Standard Architecture (ISA) bus
28
also is coupled to the PCI bus
22
via a PCI/ISA bridge
30
. A hard drive
32
and an input device
34
, such as a keyboard, game adaptor, mouse, or microphone, are coupled to the ISA bus
28
. The ISA bus
28
is an expansion bus used to separate additional functions from the functions executed over the processor bus
12
. Typical ISA buses currently operate at clock speeds between 6 MHz and 8.33 MHz.
As computer devices have become more sophisticated and faster, it has become more difficult for the computer buses, such as the processor bus
12
, the PCI bus
22
and the ISA bus
28
to keep up with the increased rate of data flow requested by the various computer devices. Whenever the graphics controller
24
, hard drive
32
or input device
34
requests access to the system memory
17
, the request must be transmitted across the PCI bus
22
as well as the processor bus
12
. As such, the performance of the computer system
10
can be limited by the throughput of the processor bus
12
, the PCI bus
22
, and the ISA bus
28
. As the speed of the computer devices continues to increase, the dependence of the computer performance upon the delay caused by sharing the computer bus resources becomes more acute.
In addition to the increased speed of current computer devices, the computer buses must be able to handle an increased number of computer devices. For example, many current computer systems have Compact Disc-Read Only Memory (CD-ROM) drives, local area network (LAN) connectors, modems, plural microprocessors, high speed redundant array of inexpensive disks (RAID) controllers and fiber optic network connectors, in addition to the standard computer devices shown in FIG.
1
. Each new computer device or peripheral added to the computer must share the same limited bus resources.
A device which contends for the shared bus resource is referred to as a bus mastering device. Each bus mastering device may have different operating characteristics than the others. Such operating characteristics include the speed at which the device operates and resource usage patterns. Only one of the bus mastering devices on the PCI bus
22
may use the PCI bus
22
at any one time. If a device wants to carry out a transaction over the PCI bus
22
, it must first be assigned control of the PCI bus
22
by a bus arbiter
21
. Therefore, when one of the bus mastering devices desires control of the PCI bus
22
, it sends a request to the bus arbiter
21
. If the bus is idle, the bus arbiter
21
assigns control of the PCI bus
22
to the device to complete one transaction. After completing the transaction, the device must return control of the PCI bus
22
to the bus arbiter
21
. If the bus mastering device has additional bus transactions to complete, it may once again request control of the bus.
In prior art systems, each bus mastering device is given equal access to the PCI bus
22
. The bus arbiter
21
cycles through a circular priority regime in which each device is in turn given priority over all others if it has a transaction to complete. For example, if there are four bus mastering devices on a bus, the bus arbiter
21
assigns a priority ranking to the devices in the pattern such as 0, 1, 2, 3, 0, 1, 2, 3 . . . with the priority rank assigned to each device rotating each time that any device accesses the bus. If the highest priority device does not have a transaction to complete, the control of the PCI bus
22
may be passed to the device with the next highest priority which has a transaction to complete.
As technology advances, some bus mastering devices continue to have increasing operating speeds and are, therefore, able to transfer large amounts of data quickly. Other devices have more limited operating speeds. In addition, the operation associated with certain device consistently entails the transfer of large blocks of data while other devices generate smaller more sporadic blocks of data. Therefore, in a computer system, each bus is likely to be serving requests from a set of bus mastering devices with a large variety of capabilities and requirements.
As the need for computer speed continues to increase, it is advantageous to promote the efficient use of the system resources which are available. The prior art bus arbitration scheme may provide an efficient allocation of resources in a system in which equally performing bus mastering devices request the use of system resources in a similar and consistent manner. However, in reality, the speed at which the bus mastering devices are capable of operating can vary by an order of magnitude. In addition, the usage pattern for the devices, in terms of the frequency of the requests and the number of consecutive requests which are received from any one device, may vary from device to device. Under these operating conditions, the uniform arbitration scheme of the prior art does not promote the efficient use of system resources. The slower devices with large blocks of data to transfer can interfere with the transfer of data from faster devices. Therefore, when the bus resources are not sufficient to service the needs of the multiple devices which are requesting access to the bus, just one slow device may significantly decrease the amount of data transferred over the bus.
In addition, the usage pattern of certain devices can vary as a function of time. For example, a RAID controller may be very active during a period of intensive file transfer and, yet, may lie inactive for great periods of time under normal operation. The prior art bus arbitration scheme does not account for usage patterns or variations in the usage patterns over time and, thus, does not promote an efficient use of system resources.
Therefore, there has been a long felt need in the industry to have a means and method of bus arbitration which promotes the efficient use of system resources.
SUMMARY OF THE INVENTION
The bus arbitration system and method arbitrates bus access based upon the performance characteristics of the devices. Each device is allowed to access the bus in approximate proportion to a desired weighted bandwidth. The desired weighted bandwidth reflects performance abilities and requirement of the devices. Access to the bus is also governed by reference to a priority ranking to prevent the faster devices from monopolizing the bus to the exclusion of the slower devices.
In one embodiment, each device is initially assigned a current weighted bandwidth equal to the desired weighted bandwidth and is also assigned a priority ranking. The bus arbiter grants access to the bus to the requesting device with the highest priority rank regardless of the current or desired value of the corresponding weighted bandwidth. Each time that a device is granted access to the bus, the value of its current weighted bandwidth is decremented. If the value of the dec
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