Method and apparatus for effecting multiple error correction in

Details Method and apparatus for effecting multiple error correction in Method and apparatus for effecting multiple error correction in

1990-06-08

1992-11-17

Beausoliel, Robert W.

Excavating

371 22, G06F 1200

Patent

active

051649446

ABSTRACT:
A memory system provides a method for error detection and correction. Large data words are divided into multiple error correction zones. One zone from each of two or more words are combined to form an error domain. Address bits are also included in the domains. Check bits are generated from the data bits in each domain and stored with the data. During data retrieval, each domain is processed separately, generating a syndrome for each domain. The syndromes provide indication of bit errors, allowing the correction of a single-bit error in each domain. Multiple-bit errors may thus be corrected within each word using a single-bit error correction code. Data are distributed in physical memory so that, within each domain, no more than one data bit is stored in the same memory device. This method provides full error correction capability in the presence of a catastrophic memory package failure, so long as failures in multiple packages do not cause multiple errors within a single error correction domain. During both read and write operations, error correction code processing may be performed in parallel for multiple domains, enhancing performance.

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"Byte-Oriented Error-Correcting Codes for Semi-Conductor Memory System," Chem. The XIV International Conference on Fault-Tolerant Computing, Kissimmee, USA, Jun. 20-22, pp. 84-87.

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