Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1998-02-27
2000-04-18
Baker, Stephen M.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
714763, 714772, G06F 1110
Patent
active
060528184
ABSTRACT:
An apparatus and method in which ECC bus protection capability can be generated on a memory card in conjunction with a computer system with a built-in ECC capability to reduce data transmission errors. Data generated by the system is transmitted to the card and stored in DRAMs. On a read cycle, the card generates a set of checkbits which are sent to the system on a checkbit bus. The system generates a set of checkbits from the data read from the memory card and compares these checkbits with those received from the memory card. A mismatch indicates transmission error on the bus(s) during a read cycle. Any correctable error is corrected. Data is invalidated if an uncorrectable error is detected. In another embodiment checkbits generated by the system during a write cycle are transmitted to the card an checkbits are generated by the card. These two sets of checkbits are compared and if there is a mismatch data is either flagged as bad or corrected. Furthermore, in one embodiment, if the memory card does "not know" in advance the type of ECC or H-matrix code resident in the computer system, the card has the capability to determine what H-matrix code is resident and set up a corresponding H-matrix.
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Dell Timothy J.
Faucher Marc R.
Hazelzet Bruce G.
Baker Stephen M.
Hogg William N.
International Business Machines - Corporation
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