Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2001-04-05
2003-12-16
Kim, Hong (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S094000, C365S189011, C365S230010, C713S320000, C711S202000
Reexamination Certificate
active
06665769
ABSTRACT:
FIELD AND BACKGROUND OF THE INVENTION
This invention relates to the programming of an N-bit memory array, such as an EEPROM array, whose cells are individually programmable by bits exhibiting a predetermined one of two complementary logic states. More particularly, this invention relates to methods and apparatus for assuring that no more than a predetermined number K of the cells of such array are simultaneously programmed to prevent overloading of the array power supply.
One technique of this general type is described in U.S. Pat. No. 5,644,531, issued to Kuo et al. on Jul. 1, 1997. The cells of an N-bit memory array are divided into groups to be programmed, and the groups are switched based in part on the location, as well as the number, of the programming bits to be programmed within an incoming N-bit programming byte. The need to create and switch among bit groups results in inefficient programming.
SUMMARY OF THE INVENTION
An improved way of efficiently programming an N-bit memory array while taking into account the power supply-induced limitations mentioned above is afforded by the method and apparatus of the present invention. This technique employs dynamic masking of the array in such a manner that creating cell groups and switching among such are not necessary.
When the number of programming bits in an incoming byte exceeds K, the mask functions to map the bit pattern of the incoming byte into sequential N-bit auxiliary bytes. The first auxiliary byte retains the bit pattern of the incoming byte up to the Kth programming bit, and the remaining bit positions of the first auxiliary byte exhibit a state complementary to the programming bits. The second auxiliary byte retains the bit pattern of the incoming byte starting with the first location after the Kth programming bit and continuing up to the Kth additional programming bit (if any); all remaining bit positions of the second auxiliary byte (including the bit positions that contained programming bits in the first auxiliary byte) exhibit the complementary state. Further auxiliary bytes can be created to accommodate all K programming bits if the first and second auxiliary bytes do not account for all the programming bits in the incoming byte (e.g., where K=3, N=8, and all bits in the incoming byte are programming bits).
The masking arrangement of the invention is adaptable for applications beyond programming memory arrays. In one more generalized embodiment, the mask functions to map successive subsets of data segments into a succession of N-bit auxiliary bytes none of which has more than an individually selectable number of bits exhibiting a predetermined one of two complementary logic states.
REFERENCES:
patent: 4760555 (1988-07-01), Gelsomini et al.
patent: 4761764 (1988-08-01), Watanabe
patent: 5361343 (1994-11-01), Kosonocky et al.
patent: 5508968 (1996-04-01), Collins et al.
patent: 5530803 (1996-06-01), Chang et al.
patent: 5644531 (1997-07-01), Kuo et al.
patent: 5940332 (1999-08-01), Artieri
Cohen Zeev
Edan Mori
Eitan, Pearl, Latzer & Cohen Zedek LLP
Kim Hong
Saifun Semiconductors Ltd.
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