Electrical computers and digital processing systems: processing – Processing control – Instruction modification based on condition
Reexamination Certificate
2007-07-23
2010-10-19
Petranek, Jacob (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Instruction modification based on condition
C708S523000
Reexamination Certificate
active
07818550
ABSTRACT:
One embodiment of a processor includes a fetch stage, decoder stage, execution stage and completion stage. The execution stage includes a primary execution stage for handling low latency instructions and a secondary execution stage for handling higher latency instructions. A detector determines if an instruction is a high latency instruction or a low latency instruction. If the detector also finds that a particular low latency instruction is dependent on, and destructive of, a corresponding high latency instruction, then the secondary execution stage dynamically fuses the execution of the low latency instruction together with the execution of the high latency instruction. Otherwise, the primary execution stage handles the execution of the low latency instruction.
REFERENCES:
patent: 5303356 (1994-04-01), Vassiliadis
patent: 5504932 (1996-04-01), Vassiliadis
patent: 5732234 (1998-03-01), Vassiliadis
patent: 5819067 (1998-10-01), Lynch
patent: 5872948 (1999-02-01), Mallick et al.
patent: 5892698 (1999-04-01), Naffziger
patent: 6571266 (2003-05-01), Bass
patent: 6813626 (2004-11-01), Chng
patent: 6889318 (2005-05-01), Wichman
patent: 7225323 (2007-05-01), Siu
patent: 2004/0128483 (2004-07-01), Grochowski et al.
patent: 2008/0133880 (2008-06-01), Pinto et al.
Chen—“Fusing Instructions to Reduce Resource Usage in If-Converted Regions”, 5thWorkshop on EPIC Architectures and Compiler Technology (Mar. 26, 2006).
Gelas—“Intel Core versus AMD's K8 Architecture”, www.anandtech.com (May 1, 2006).
Gran—“An Enhancement for a Scheduling Logic Pipelined Over Two Cycles”, IEEE (2006).
Hu—“Using Dynamic Binary Translation to Fuse Dependent Instructions”, Proceedings of the International Symposium on Code Generation and Optimization, IEEE(2004).
Jackson—“Inside Intel's Core Duo processors”, Personal Computer World (Sep. 11, 2006).
Petric—“Reno: A Rename-Based Instruction Optimizer”, (Dec. 9, 2004).
Pochinsky—“The Blue Gene, GCC and Lattice QCD: A Case Study”, Journal of Physics (2006).
Wechsler—“Inside Intel® Core™ Microarchitecture: Setting New Standards for Energy-Efficient Performance”, Technology @ Intel Magazine (Mar. 2006).
Gerhardt Diana
International Business Machines - Corporation
Kahler Mark P
Petranek Jacob
LandOfFree
Method and apparatus for dynamically fusing instructions at... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for dynamically fusing instructions at..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for dynamically fusing instructions at... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4164860