Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
1999-11-23
2003-09-23
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S129000, C711S209000, C710S052000, C710S056000, C710S104000
Reexamination Certificate
active
06625708
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to memory technologies generally and particularly to defining line buffer configurations in a memory system.
BACKGROUND OF THE INVENTION
Since programs tend to reuse data and instructions they have used recently, processors executing such programs often utilize cache memory to further enhance their overall performances. A system designer typically uses the fastest memory available in the system's memory hierarchy, such as Static Random Access Memory (SRAM), for cache memory. Since SRAMs use more circuits per bit than a slower type of memory, such as Dynamic Random Access Memory (DRAM), to prevent the information from being disturbed when read, SRAMs tend to have the same access time and cycle time. “Line buffers” refer to portions of the described cache memory and usually store intermediate results within a data processing system. For example, an image processing system may employ line buffers for storing some interpolation results of the system's image processing routines. Traditionally, line buffer configurations are straightforward. Frequently a system architect of data processing systems would predefine the size and the number of line buffers according to particular designs of the systems.
However, when the data processing systems require utilization of various types of line buffers at different occasions, the previously discussed approach of predetermining the size and number of line buffers becomes expensive and impractical. For instance, when an image processing system predefines two line buffers with certain sizes to store X bytes of incoming video data, as long as the incoming data do not exceed X bytes, these line buffers may still permit the system to generate accurate end results. On the other hand, when the incoming video data exceed X bytes, these line buffers alone may become unable to correctly handle these excess data. Furthermore, remedying this described scenario may include additional cache memory or additional circuit logic and thus increases the cost of the image processing system.
Therefore, a method and apparatus is needed to dynamically define line buffer configurations in a memory.
SUMMARY OF THE INVENTION
A method and apparatus of defining a line buffer configuration in a memory is disclosed. In one embodiment, the method and apparatus receives input data information and mode information, proceeds to select a type of the line buffer configuration according to the mode information, and dynamically generates addresses for the selected type of line buffer configuration in the memory according to the input data information.
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Chace Christian P.
Sparks Donald
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