Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
1999-12-28
2003-05-20
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S026000, C327S281000
Reexamination Certificate
active
06566903
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to performance control of integrated circuits. More specifically, the present invention relates to an apparatus, method, and system for dynamically controlling the performance of buffer circuits under different performance conditions.
BACKGROUND OF THE INVENTION
Buffer circuits, for example input/output (I/O) buffers are widely used to facilitate the transfer of data and signals from one component or circuit to another component or circuit within a given system. As an example, a processor unit such as a microprocessor may contain a buffer unit that is used to transmit data to and receive data from other components such as memory components or chipset units via buses. Accordingly, the performance of the buffer unit directly affects the performance of the system component and the system as a whole since the speed of data transfer between the different components in the system is one of the factors in measuring the overall performance of any given system or circuitry.
The performance of a buffer circuit or an electronic component can vary based upon variations in the performance conditions or parameters including variations in manufacturing process, operating voltage, and operating temperature, etc. In general, some of the performance characteristics of the buffer circuit or the electronic component that may change due to variations in the operating conditions and process include the clock to output time, input drive current, and output drive current, etc. The term “fast” corner or “FFFF” corner is used to refer to the operation of the buffer circuit at its fastest, strongest performance. The term “slow” or “RSSS” corner is used to refer to the operation of the buffer circuit at its slowest, weakest performance.
Some of the parameters that are used to measure the performance of a buffer circuit are the “TCO_MIN” and “TCO_MAX”. TCO_MIN is defined as the minimum clock to output time or the time required in the FFFF corner for a signal to move to the output of the final driver in the buffer with reference to the clock edge which latches the signal into the buffer. The TCO_MAX is defined as the maximum clock to output time or the time required in the RSSS corner for a signal to move to the output of the final driver in the buffer with reference to the clock edge which latches the signal into the buffer. To increase the speed and thus the overall performance of a buffer circuit, the designer would want to design the buffer with high TCO_MIN and low TCO_MAX in order to satisfy the timing equations including the setup equation and the hold margin equation. However, the development of buffer circuits has been limited by the fact that TCOMIN and TCOMAX could not be improved simultaneously on the same design because to improve either of them deteriorate the other. As mentioned above, the RSSS corner and the FFFF corner are the extreme corners in the design simulation. The buffer circuits tend to be slow in the RSSS corner thus making it difficult for the setup equation to be satisfied. In the FFFF corner, however, the buffer circuits can be too fast to satisfy the hold margin equation.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a method is provided in which an input signal is received at a first node of a buffer circuit. The propagation of the input signal from the first node to a second node in the buffer circuit is delayed by a delay period based upon a first control input. The delay period is adjusted by a factor based upon a second control input.
REFERENCES:
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5712582 (1998-01-01), Yokota et al.
patent: 6009487 (1999-12-01), Davis et al.
patent: 6072747 (2000-06-01), Yoon
patent: 6268753 (2001-07-01), Sandusky
Jahan Mirza
Mandal Subrata
Blakely , Sokoloff, Taylor & Zafman LLP
Chang Daniel D.
Intel Corporation
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