Method and apparatus for dynamically adjusting the clock speed o

Electrical computers and digital processing systems: support – Computer power control

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Details

713320, 713322, 713500, 713501, 713600, 713601, G06F 1300

Patent

active

060790229

ABSTRACT:
A dynamic clock control comprising an idle detector and a variable speed clock supply. The idle detector detects when an idle condition appears on the bus and sends an appropriate control signal to the variable speed clock supply. The clock supply, which supplies clocking signals for the bus components coupled to the bus, changes the frequency of the clocking signals from a faster, full-speed frequency to a lower frequency. When the bus becomes active, the idle detector causes the clock supply to supply clocking signals at the original full-speed frequency. With the apparatus and method of the present invention, the frequency of the clocking signals supplied to the bus components can be dynamically controlled without user intervention. Since for many bus components, power consumption is proportional to clocking frequency, a significant power savings is obtained for the overall bus system.

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