Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-07-13
1999-01-12
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711204, 711213, 711118, 711154, 364707, 365227, 39575003, 39575005, 39575006, G06F 938, G06F 132
Patent
active
058601066
ABSTRACT:
An apparatus and method for dynamically adjusting the power/performance characteristics of a memory subsystem. Since the memory subsystem access requirements are heavily dependent on the application being executed, static methods of enabling or disabling the individual memory system components (as are used in prior art) are less than optimal from a power consumption perspective. By dynamically tracking the behavior of the memory subsystem, the invention predicts the probability that the next event will have certain characteristics, such as whether it will result in a memory cycle that requires the attention of a cache memory, whether that memory cycle will result in a cache memory hit, and whether a DRAM page hit in main memory will occur if the requested data is not in one of the levels of cache memory. Based on these probabilities, the invention dynamically enables or disables components of the subsystem. By intelligently adjusting the state of these components, significant power savings are achieved without degradation in performance.
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Steven A. Przybylski, "Cache and Memory Hierarchy Design" 1990, Morgan Kaufmann Publishers, INC.
Domen Stanley J.
Gunther Stephen H.
Idate Dileep R.
Thangadurai George
Chan Eddie P.
Intel Corporation
Kim Hong C.
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