Method and apparatus for dynamic timing of memory interface...

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing

Reexamination Certificate

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C713S503000, C711S168000

Reexamination Certificate

active

07047384

ABSTRACT:
A method and apparatus for using different timings to latch signals sent by two memory devices of identical design to compensate for differences in the lengths of conductors across which the signals must propagate.

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Microsoft Computer Dictionary, 5th ed. 2002 Microsoft Press, p. 19.

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