Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1996-12-11
2001-05-29
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S083000, C326S114000, C326S030000
Reexamination Certificate
active
06239619
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data bus transfers and more particularly to dynamic termination logic of data buses to improve performance of the data buses.
2. Description of the Related Arts
As computer technologies continue to grow in leaps and bounds, users of the computer technologies have an insatiable desire for faster systems in ever smaller packages. One area of a system that is often a weak link to an otherwise much faster system is the data bus. The data bus provides transfers of data in the form of electrical signals from one subsystem to another. Often times the data bus of a system gets overwhelmed with data transfers and becomes the bottle neck of the system.
In a high performance bi-directional data bus design, the data transfer bottle neck problem is compounded by multiple devices transferring data on the same data bus and the transfer of data in two directions. Certain functions performed by a computer system such as driving an address bus utilize bi-directional buses. A typical bi-directional bus design has at least two end-drivers, each located to one end of the bi-directional data bus and is configured for wire-oring of data signals on the data bus. In the wire-or configuration, either end-driver is able to drive data signals on the data bus. When the end-drivers are inactive, the data bus is pulled-up to a logic high state, “1”. When an end-driver is active and driving the data bus, the data bus is at the logic low level, “0”.
As the end-drivers transition between inactive and active states of operation, switching wave signals are generated. If the switching wave signals are not terminated, reflections of the switching wave signals occur that will cause ringing on the data bus. The ringing causes the data signals on the data bus to be unsettled. An unsettled data bus produces unstable data. As the ringing from the reflections eventually settles, the data on the data bus stabilizes to a steady logic. Ringing on the data bus is undesirable because the ringing reduces the speed at which data signals are transferred on the data bus. Time wasted waiting for the data bus to settle from the ringing can be best used for additional data transfers.
Present data bus designs attach a termination resistor at each of the data bus to terminate the switching wave signals. The termination resistors serve a dual purpose of terminating the switching wave signal and providing a pull-up signal to produce a logic high state on the data bus when the end-drivers are inactive. The end-drivers are typically open drain or open collector transistors depending on whether the transistors are formed using CMOS (complementary metal oxide silicon) or bipolar processes. To properly terminate the switching wave signals, the resistive value of the termination resistors are set to the characteristic impedance of the data bus. No reflections occur when the ends of a data bus are properly terminated with termination resistors whose values equal to the characteristic impedance of the data bus.
Take for example the data bus with two end-drivers and two termination resistors attached to the ends of the data bus. When one end-driver becomes active while the other is inactive, a negative switching wave signal (transition from an initial high logic state to a low logic state) generated from the active end-driver travels to the end of the data bus and is terminated without reflections by the termination resistor at the end of the data bus. However, during operations of the data bus there are instances when back to back switching occurs with the end-drivers. Back to back switching occurs when both end-drivers are simultaneously switching between active and inactive states of operation. As one end-driver switches from inactive state to active state, a negative switching wave signal (transition from a high logic state to a low logic state) is generated. As the other end-driver switches from active state to inactive state, a positive switching wave signal (transition from a low logic state to a high logic state) is generated. The negative switching wave signal terminates when it reaches the termination resistor at the end of the data bus, but the positive switching wave signal produces a reflection from the active end-driver which has a resistance other than the characteristic impedance of the data bus. A wire-or glitch results from the reflection of the positive switching wave signal. The wire-or glitch causes ringing on the data bus and produces unsettled data signals on the data bus. Time is wasted waiting for the ringing on the data bus to settle.
Moreover, the data buses are often formed as traces on printed circuit boards which route the data buses to the various circuit components of a sub-system. The printed circuit boards of a computer may include tens of data buses coupling the multitude of the circuit components together. There are also a plurality of mid-drivers in open drain or open collector configurations placed between the end-drivers to provide data bus access for the circuit components of the subsystem. Because termination resistors are placed at the ends of a data bus, present data bus designs attach the resistors externally on the printed circuit board. Valuable areas of the printed circuit board that can be used for additional circuit components and circuitry are wasted.
Therefore, it is desirable to provide an apparatus and methods of operating the same which improve settling time of data buses and eliminate placement of space-wasting external termination resistors on printed circuit boards and other subsystems of a computer system.
SUMMARY OF THE INVENTION
The present invention provides an apparatus for dynamic termination of data buses and methods for operating the same which result in improved settling time of data signals on the data bus. The novel data bus design is based on data bus drivers having dynamic termination logic to improve effectiveness of terminating data signals on a data bus. Thus, according to one aspect of the invention, a bi-directional data bus for wire-or data transfers comprises a first end-driver coupled to a first end of the data bus configured to drive the first end of the data bus with a first signal. A second end-driver coupled to the second end of the data bus is configured to dynamically terminate the first signal from the first end-driver. The second end-driver includes a pull-up transistor with a resistive value of the characteristic impedance of the data bus and a pull-down transistor with a resistive value of the characteristic impedance of the data bus. The termination resistors are integrated with the second end-driver and act to terminate the first signal. Thus, regardless of the state of the second end-driver being active or inactive, a resistive value of the characteristic impedance is coupled to the data bus to terminate the first signal from the first end-driver.
According to another aspect of the invention, the second end-driver drives the data bus with a second signal and the first end-driver dynamically terminates the second signal from the second end-driver. The first end-driver includes a pull-up transistor with a resistive value of the characteristic impedance of the data bus and a pull-down transistor with a resistive value of the characteristic impedance of the data bus. The termination resistors are integrated with the first end-driver. Thus, regardless of the state of the first end-driver being active or inactive, a resistive value of the characteristic impedance is coupled to the data bus to terminate the second signal from the second end-driver.
According to another aspect of the invention, the first end-driver and the second end-driver simultaneously dynamically terminate the first and the second signals. During back to back switching of the first end-driver and the second end-driver which occurs when the end-drivers switch on consecutive synchronous clock cycles, the received first signal at the second end-driver and the received second signal at the first end-driver dyn
Amir Chaim
Doblar Drew George
Nguyen Trung Thanh
Starr Jonathan Eric
Tsai Derek Shuntao
Chang Daniel D.
Park & Vaughan LLP
Sun Microsystems Inc.
Tokar Michael
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