Method and apparatus for dynamic system-level frequency scaling

Details Method and apparatus for dynamic system-level frequency scaling Method and apparatus for dynamic system-level frequency scaling

2011-01-04

2011-01-04

Connolly, Mark (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S600000

Reexamination Certificate

active

07865749

ABSTRACT:
A method and apparatus for changing a clock frequency in a system (10) comprising a plurality of synchronous integrated circuit chips (12, 14, 16), and a circuit (20) for implementing the frequency change. The method includes: detecting a change in processing requirements in one of the plurality of synchronous integrated circuit chips; notifying the plurality of synchronous integrated circuit chips that a clock frequency change is to occur; achieving a quiescent bus state in each of the plurality of synchronous integrated circuit chips; notifying the plurality of synchronous integrated circuit chips that the clock frequency change can occur; and changing the clock frequency of the plurality of integrated circuit chips.

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Kozierok, Derived System Clocks, The PC Guide, Apr. 17, 2001, Version 2.2.0, pp. 1-2.

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