Method and apparatus for dynamic prefetch buffer...

Details Method and apparatus for dynamic prefetch buffer... Method and apparatus for dynamic prefetch buffer...

2006-11-21

2006-11-21

Bragdon, Reginald (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S133000, C711S144000, C711S170000

Reexamination Certificate

active

07139878

ABSTRACT:
A memory controller and method thereof configures a prefetch buffer dynamically for interfacing between multiple bus masters of different burst support and multiple memories having different characteristics. A line size of at least a portion of the prefetch buffer is modified based upon the memory controller receiving a read request from one of the bus masters. An adaptive method to optimally replace prefetch buffer lines uses prioritized status field information to determine which buffer line to replace.

REFERENCES:
patent: 5958040 (1999-09-01), Jouppi
patent: 6085291 (2000-07-01), Hicks et al.
patent: 6529998 (2003-03-01), Yochai et al.
patent: 6636927 (2003-10-01), Peters et al.
patent: 6718452 (2004-04-01), Wojcieszak et al.
patent: 2004/0068615 (2004-04-01), Chaudhari et al.

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