Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Patent
1996-12-02
1999-07-27
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
39580014, 711 5, 711171, G06F 1200
Patent
active
059308273
ABSTRACT:
A method and apparatus for dynamically allocating system memory using a binary tree organized in an address and size dependent manner. Within the prior art, dynamic memory allocation methods were not portable to virtual memory addressing systems wherein local memory and system memory were joined in a continuous region of linear addresses. The allocation method of the present invention utilizes a binary tree of free memory block headers, corresponding to free memory blocks. Each free memory block header has an address field and a translation table field. The address field corresponds to a virtual address of the free memory block. The translation table field points to an entry within a translation table that is used to map the virtual address to a block in system memory.
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Cabeca John W.
Intel Corporation
Mikkola Laura L.
Ransom David
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