Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-01-27
2002-05-28
Thai, Xuan M. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S052000, C710S057000, C710S058000, C710S310000, C709S250000
Reexamination Certificate
active
06397287
ABSTRACT:
a. Field of the Invention
The present invention relates to architectures of network adapters. In particular, the present invention relates to architectures which optimize the transmission of packets or frames of data across a communication network.
b. Description of Related Art
In a communications network such as a LAN or a WAN, a network adapter manages the transmission and reception of data packets by transferring data between the network and a host computer system memory. The system memory is used by several different devices including the system CPU, Input/Output devices and storage devices as well as the network itself. The network adapter typically accesses the system memory through a shared host system expansion bus, such as a PCI bus.
Network adapters therefore play a key role in the efficiency of the transfer of data between a computer system and a network. Typically, a network adapter transmits data onto a network from a host computer by reading the data out of the host system memory, through a host bridge device, across the expansion bus, into a transmit buffer in the network adapter and then out to the network. This process of moving data from system memory to the adapter transmit buffer can be referred to as a “download”. Similarly, data received from the network enters a receive buffer in the network adapter, and from there is moved across the expansion bus, through the host bridge and into system memory buffers. This process can be referred to as an “upload”.
Given the ever increasing demands on computer systems and networks to operate more quickly and efficiently, it has become paramount that network adapters optimize the time during which they have control of an expansion bus to perform uploads and downloads.
One method of optimizing the bus tenure is to maximize burst length. For, in a typical computer system, data bytes are moved across the expansion bus and to the network in groups called bursts. A burst is defined as the number of bytes which can be moved across the expansion bus within the adapter's tenure on the bus. The burst length is determined by the adapter design, the host bridge design, and the instantaneous demand for the expansion bus. In general, it is optimal if larger bursts are utilized because they increase the efficiency of the expansion bus and, in a high demand environment, allow greater data throughput for each device and for the system as a whole. Typically, the size of these bursts is limited physically by several of the aforementioned devices. First, the particular host bridge implementation will possess a maximum burst length capability, related to the size of its internal buffering and to its internal architecture. Second, the internal buffering of the network adapter itself will similarly limit the maximum burst length capability. Generally speaking, the internal buffering of the network adapter is usually smaller than that of the typical host bridge implementation, and thus the maximum burst length is usually thereby limited. For instance, in a cut-through network adapter, a data packet is copied through the adapter into the shared memory. In order to accomplish this, the adapter buffers the data in a first-in, first-out queue (FIFO) in the adapter. A typical FIFO may, for example, be 128 to 1024 bytes while data packets may be as large as 4500 bytes. This is true because of a desire to minimize the costs of network adapters—which are typically implemented by application specific integrated circuits (ASICS)—by limiting the amount of memory available for the internal transmit and receive buffers.
Beyond maximizing burst length, another way of optimizing network data throughput is to transmit data onto the network while simultaneously moving the data from system memory across the expansion bus. This also allows the adapter to implement smaller transmit and receive buffers, since there does not need to be a large enough buffer to hold an entire maximum-sized network data packet as discussed above. However, having buffers smaller than a packet introduces the problem of transmit underruns and receive overruns.
A transmit underrun can occur if an adapter is transmitting a packet on to the network, out of its buffer, while simultaneously moving that packet from system memory into its transmit buffer. If the adapter experiences a momentary interruption in the flow of data from system memory, the transmit buffer can go empty, resulting in incorrect data being transmitted to the network. Similarly, a receive overrun occurs if an adapter is receiving a packet from the network, and it is temporarily unable to move the data at sufficient speed across the expansion bus into system memory. Eventually, the receive buffer fills up, and any subsequent data from the network is lost. Both transmit underruns and receive overruns result in degraded performance in the network, and are to be avoided.
Therefore, what is needed is a method and an apparatus which further optimizes the transfer of data between a host computer system and a network without needlessly increasing the size, and cost, of network adapter buffers, and without subjecting the system to performance degrading data overruns and underruns.
2. SUMMARY OF THE INVENTION
As discussed above, the optimization of data transfer between a host system and a network is an important factor in the design of computer networks such as local area networks (LAN) and wide area networks (WAN). The optimization of data transfer may include maximizing the amount of data transferred to/from the host system during a particular bus tenure while simultaneously minimizing the number of underruns and overruns in the system. As will be set out below in further detail, the present invention includes a method and apparatus for optimizing the transfer of data between a host computer system and a network without needlessly increasing the size, and cost, of network adapter buffers, and without subjecting the system to performance degrading data overruns and underruns.
In one embodiment, the present invention is characterized as a method for transferring data between a host computer and a network medium coupled to the host computer—the host computer includes an expansion bus and a network adapter device coupled to the expansion bus and to the network medium. In this embodiment, the method includes transferring data between a buffer memory in the network adapter and the network medium, and generating a first buffer data signal in response to the amount of data present in the buffer memory. The method further includes generating a second buffer data signal in response to the length of previous transfers of data between the host computer and the network medium. Accordingly, the second buffer data signal represents the amount of data in the buffer at the time when the expansion bus should be requested by the network adapter device to optimize a data transfer between the network adapter and the host computer. The method also includes the steps of asserting a bus request signal to the host computer in response to the first and second buffer data signals and finally transferring data between the host computer and the buffer memory over the expansion bus.
In one instance of this embodiment, the step of asserting the bus request signal comprises providing the first and second buffer data signals to a dynamic bus request control logic, comparing the first buffer data signal with the second buffer data signal, and generating the bus request signal when the value of the first buffer data signal satisfies a logical relation to, such as is one of greater than and less than, the second buffer data signal.
In still another embodiment, the method is further defined in that generating the second buffer data signal is responsive to the size of data bursts transferred between the host computer and the buffer memory. In one instance of this embodiment, generating the second buffer data signal includes monitoring the size of each data burst transferred between the host computer and the buffer memory and updating the value of the second
Brown David Robert
Connery Glenn W.
3Com Corporation
McDonnell & Boehnen Hulbert & Berghoff
Thai Xuan M.
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