Method and apparatus for dynamic allocation of registers for int

Details Method and apparatus for dynamic allocation of registers for int Method and apparatus for dynamic allocation of registers for int

1996-11-27

1998-09-08

Donaghue, Larry D.

395563, 395393, G06F 938

Patent

active

058059164

ABSTRACT:
The present invention relates to a multiple stage execution unit for executing instructions in a microprocessor having a plurality of rename registers for storing execution results, an instruction cache for storing instructions, each instruction being associated with a rename register, a sequencer unit for providing an instruction to the execution unit, and a data cache for providing data to the execution unit. In one version, the execution unit includes a first stage which generates an intermediate result from the data according to an instruction; a means for providing a first portion of the intermediate result to an intermediate register; a means for providing a second portion of the intermediate result to a rename register associated with the instruction; a means for passing the first portion from the intermediate register to a second stage of the execution unit; a means for passing the second portion from the rename register to the second stage of the execution unit; wherein the second stage of the execution unit operates on the first and second portions according to the instruction.

REFERENCES:
patent: 5386375 (1995-01-01), Smith
patent: 5465373 (1995-11-01), Kahle et al.
patent: 5584037 (1996-12-01), Papworth et al.
patent: 5646875 (1997-07-01), Taborn et al.

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