Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1997-10-20
2001-01-09
Myers, Paul R. (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C711S154000, C711S167000
Reexamination Certificate
active
06173353
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to digital data processing systems and, more specifically to a method and apparatus for increasing the speed of burst memory transactions within a computer system.
2. Background Information
As the computer revolution has progressed, the quest of computer hardware developers has been to develop computer systems exhibiting more processing power and faster performance. In order to increase the speed of computer systems, developers place great emphasis in efficiently using the available clock cycles of the central processing unit (CPU) to execute the necessary instructions.
Pipeline burst static memory units (memory) are integrated into the majority of the CPU boards that are now manufactured. Data is stored to and retrieved from addressable storage locations within the memory, and transferred to and from the CPU via a data bus. The memory also communicates with the CPU over an address bus, which is used by the CPU to access the storage locations of the memory.
For read transactions, a read address is transferred from the CPU to the memory over the address bus. Later, corresponding data is transferred from the memory to the CPU. A burst read transaction uses one clock cycle to transfer an address packet from the CPU to the memory; and the next four clock cycles to transfer the corresponding data packets from the memory to the CPU. FIG.
1
a
illustrates a clock diagram of a burst read transaction.
For write transactions, a write address is transferred from the CPU to the memory over the address bus, while data is transferred from the CPU to the memory over the data bus at the same time. A burst write transaction uses one clock cycle to transfer both the address packet and the first data packet from the CPU to the memory, and uses the next three clock cycles to transfer the remaining data packets. FIG.
1
b
illustrates a clock diagram of a burst write transaction.
While a burst transfer is in progress, the address bus is unused for much of the duration of the transaction. During burst write transactions the address bus is unused for three clock cycles while data is being transferred; and on burst read transactions, the address bus is unused for four clock cycles while data is being transferred. Thus data processing systems using these memory access schemes are not making efficient use of the address bus during burst memory transactions.
SUMMARY OF THE INVENTION
According to a first embodiment, a method for reducing the total number of clock cycles required to carry out burst memory transactions is described. During burst write transactions, a memory accepts data over an address bus during one of the three clock cycles after an address is received. In order to accept data over the address bus, the memory temporarily stores the data received over the address bus in an internal data buffer before transferring the data to an array upon completion of the write transaction. During burst read transactions, the memory transmits data over the address bus during one of the four clock cycles after the address is received. A burst write transaction is thus completed in three clock cycles instead of four. Burst read transactions are completed in four clock cycles instead of five.
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Blakely & Sokoloff, Taylor & Zafman
Myers Paul R.
Sun Microsystems Inc.
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