Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1996-11-27
1999-08-17
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
36523006, 365222, G06F 1216
Patent
active
059408510
ABSTRACT:
Method and apparatus for refreshing DRAM devices (chips) in a computer system. Each DRAM device incorporates circuitry to carry out a burst of RAS cycles during each refresh period. Three different modes are used to trigger the device into refresh. In one mode, each DRAM device incorporates a refresh timer; only one master DRAM device in the system has its refresh timer enabled. The refresh master device generates a refresh request every time the refresh timer times up. A memory controller, after receiving the request, generates an acknowledge signal when certain system conditions are met. All DRAM devices in the system monitor the refresh request and acknowledge handshake continuously. Upon detection of refresh acknowledge, each DRAM device caries out a sequence of predesignated refresh cycles. In a second mode, the DRAM devices are all strapped as refresh slaves and the refresh timer resides in the memory controller which drives the same refresh acknowledge signal low for two clock cycles when the refresh timer times-up. Upon receiving the acknowledge signal, the DRAM devices each carry out the refresh operation. In a third (self refresh) mode, each DRAM device generates a internal clock signal, which has a different frequency and phase relationship with the external clock signal, for operating its internal refresh timer and refresh logic. Each DRAM device carries out its refresh periodically without communicating to the controller or the other DRAM devices. Each of the three refresh modes is selected by externally supplied mode select signals.
REFERENCES:
patent: 4575826 (1986-03-01), Dean
patent: 5349562 (1994-09-01), Tanizaki
patent: 5430680 (1995-07-01), Parris
patent: 5559750 (1996-09-01), Dosaka et al.
Klivans Norman R.
Langjahr David
Monolithic Systems, Inc.
Swann Tod R.
LandOfFree
Method and apparatus for DRAM refresh using master, slave and se does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for DRAM refresh using master, slave and se, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for DRAM refresh using master, slave and se will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-325995