Method and apparatus for DRAM memory performance enhancement

Details Method and apparatus for DRAM memory performance enhancement Method and apparatus for DRAM memory performance enhancement

1988-10-28

1991-06-04

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Including signal comparison

365195, G11C 700

Patent

active

050220047

ABSTRACT:
A method and apparatus is disclosed for improving the performance of a digital computer by reducing the latency of read operations and increasing available write bandwidth by utilizing a subset of the address bits which are the same from one operation to the next. A faster cycle type (e.g. page mode or static column) can thereby be employed in the Dynamic Random Access Memory (DRAM) memory by eliminating the DRAM precharge and RAS address portions of the cycle.

REFERENCES:
patent: 4104719 (1978-08-01), Chu et al.
patent: 4599708 (1986-07-01), Schuster
patent: 4744062 (1988-05-01), Nakamura et al.
patent: 4931993 (1990-06-01), Urushima

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